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In advanced CMOS technology, the NBTI (negative bias temperature instability) effect results in delay degradations of PMOS transistors. Further, because of clock gating, PMOS transistors in a clock tree often have different active probabilities, leading to different delay degradations. If the degradation difference is not properly controlled, this clock skew may cause the circuit fails to function at some point later in time. Intuitively, the degradation difference can be eliminated, if we increase the active probability of the low-probability clock gates to ensure the clock gates at the same level always having the same active probability. However, this intuitive method may suffer from large power consumption overhead. In this article, we point out, by carefully planning the transistor-level clock signal propagation path, we can have many clock gates whose active probabilities do not affect the degradation difference. Based on that observation, we propose a critical-PMOS-aware clock tree design methodology to eliminate the degradation difference with minimum power consumption overhead. Benchmark data consistently show our approach achieves very good results in terms of both the NBTI-induced clock skew (i.e., the degradation difference) and the power consumption overhead.

As the process technology scaling, the tolerance to PVT (process/ voltage/temperature) variation has become a serious concern. During the post-silicon stage, ADBs (adjustable delay buffers) can be used to adjust the delay of the clock path for eliminating the clock skew. However, in fact, unless that the clock tree has a self-correcting mechanism, the clock skew caused by PVT variations still cannot be properly controlled. In this paper, we propose the first self-correcting ADB system to control the clock skew during circuit execution. Experimental results show that our design methodology can achieve very good results.

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Dual threshold voltage (dual-Vth) assignment is recognized as a useful technique to reduce the leakage power. However, as the process technology shrinks to the deep sub-micron regime, the negative bias temperature instability (NBTI) effect becomes a serious concern. The NBTI effect may cause the degradation of threshold voltage over a period of months or years. Since previous dual-Vth assignment techniques do not consider the NBTI effect, they often decrease the circuit lifetime. In this paper, we propose an NBTI-aware dual-Vth assignment algorithm. Our objective is not only to reduce the leakage power but also to maintain the lifetime of the circuit. By assigning independent candidate gates to high threshold voltage (HTV) simultaneously, in each benchmark circuit, our approach can achieve a better result with a smaller CPU time. Experimental data consistently show that our approach works well in practice.

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