Validation and test generation for oscillatory noise in VLSI interconnects

Sinha, Arnab; Gupta, Sandeep; Breuer, M.A.

doi:10.1109/iccad.1999.810664

Cited by 17 publications

(8 citation statements)

References 14 publications

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“…We believe that such noise will be present as we move into deeper sub-micron processes where transistors are much more sensitive to noise. In fact, by considering trends in process parameters it was shown that such noise will be prevalent in 0.13 m processes and beyond [10]. In [10], a 0.25 m process was used, and the magnitude of inductance had to be set to ten times its actual value before a significant undershoot occurred.…”

Section: Oscillatory Noisementioning

confidence: 99%

“…In fact, by considering trends in process parameters it was shown that such noise will be prevalent in 0.13 m processes and beyond [10]. In [10], a 0.25 m process was used, and the magnitude of inductance had to be set to ten times its actual value before a significant undershoot occurred. For the 0.18 m process used here, only twice the actual value of inductance gives rise to a significant undershoot.…”

Section: Oscillatory Noisementioning

confidence: 99%

“…We now see a great interest in the inductance associated with on-chip signal lines [3]- [6], [9], [10], [15], [17]- [22], [24], [25]. An instance of a processor failure due to inductance induced crosstalk was reported in [5].…”

mentioning

confidence: 99%

“…The effect of a crosstalk induced pulse or undershoot generated at a noise-site can propagate to a primary output or a latch input and create a logic-value error [2], [10]. The effect of crosstalk induced delay generated at a noise-site can cause a transition to propagate to a primary output or a latch input beyond the clock sampling time [2].…”

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confidence: 99%

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Validation and test issues related to noise induced by parasitic inductances of VLSI interconnects

Sinha

Gupta

Breuer

2002

IEEE Trans. Adv. Packag.

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In this paper we show the results of studies of noise induced by various combinations of parasitic capacitances and inductances. This work is based on simulating interconnects with parameters obtained from a 0.18 m process. The four kinds of noise addressed are i) crosstalk pulse; ii) crosstalk speedup and slowdown; iii) oscillatory noise; iv) combination of oscillatory noise and crosstalk pulse. We observe that the crosstalk effects induced by a combination of mutual capacitance and mutual inductance can be larger than those induced by mutual capacitance alone, even if capacitive crosstalk dominates. We observe that, for certain interconnects that are capacitively and inductively coupled, transitions in the same direction on an aggressor and victim line can cause speedup or slowdown, depending on timing parameters. A similar observation holds for transitions in opposite directions. We also observe that oscillatory noise can combine with crosstalk pulse under certain skew conditions and give rise to a large magnitude of noise. We show that inductance induced noise can be a problem in medium length interconnects. Because such interconnects can occur in combinational logic blocks, the generation of suitable vectors for test and validation of such logic blocks is of concern.We show that the magnitude of crosstalk induced pulse and delay vary nonmonotonically with variation in timing parameters of transitions at the inputs of the aggressor and victim lines. We also observe that the magnitude of inductance induced noise is affected by spot defects and variation in process parameters. We show that the value of static signals on interconnects adjacent to the aggressor and victim lines can impact the magnitude of noise and delay for both the capacitive only case and the capacitive and inductive case. In conclusion, we summarize the impact of the above observations on test and validation of inductance induced noise and delay.

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Section: Oscillatory Noisementioning

confidence: 99%

Section: Oscillatory Noisementioning

confidence: 99%

mentioning

confidence: 99%

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confidence: 99%

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Validation and test issues related to noise induced by parasitic inductances of VLSI interconnects

Sinha

Gupta

Breuer

2002

IEEE Trans. Adv. Packag.

Self Cite

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“…Aggressor alignment for the purpose of worst-case coupling noise has not been analyzed explicitly. Furthermore, simultaneous switching aggressors' inputs (with same arrival times) has been assumed as a condition resulting in WCN in some papers [3][4] [11].…”

Section: Previous Workmentioning

confidence: 99%