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In today’s embedded technology, memories are the universal components. With the onset of the deep-submicron VLSI technology, the density and capacity of the memory are growing. However, providing a cost-effective test solution for these on-chip memories is becoming a challenging task. As memory and other processing cores have been embedded deeply in system chips, the IEEE std 1500 has been suggested to facilitate the test of these core types. Whereas up to now this standard has not presented a definite solution for testing of memory cores, in this paper, we proposed a programmable IEEE 1500-compliant wrapper for applying several Mach algorithms on word-oriented memory cores to reach the desired fault coverage. The proposed wrapper is without finite-state-machine controller, and as a result, the complexity of wrapper circuitry is low and hardware redundancy is acceptable as well.

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