Utilization of cache area in on-chip multiprocessor

Oi, Hitoshi; Ranganathan, N.

doi:10.1007/bfb0094939

“…Data replication also bears resemblance to earlier work on remote data caching in conventional CC-NUMA and COMA architectures [20,9,28], which also try to retain local copies of data that would otherwise require a remote access. There are two major differences in the CMP structure, however, that limit the applicability of prior remote caching work.…”

Section: Related Workmentioning

confidence: 84%

Victim Migration: Dynamically Adapting Between Private and Shared CMP Caches

Zhang

¹

,

Asanović²

2005

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“…CMP Cache Common Features UMA [25] Shared cache (UCA) High capacity, uniformly long latency NUMA [91,93] Shared, banked, cache (S-NUCA) [83] High capacity, non-uniform latencies COMA [56,129] Private caches [67] Lowered capacity, low latency RC-NUMA [160] Adaptive private/shared NUCA [40] Partition between private/shared space VC-NUMA [108] VC-CMP [115], Victim replication [159] Victim caching R-NUMA [45] CMP-NuRapid [27] Counter-based hints for relocation AS-COMA [88] CMP cooperative caching [23] Biased replacement OS support [150] ASR [14] Selective replication Table 2.1: Corresponding Proposals for Organizing DSM Memory and CMP Caches accesses can be several times faster than remote accesses in a NUMA system, a significant amount of research was done to improve data locality via a Cache-Only Memory Architecture (COMA) that uses local memory to attract frequently used data [56,129], NUMA augmented with remote data caches or victim caches [108,160], adaptation between COMA and CC-NUMA [45,88] according to perceived memory pressure, and software techniques for page migration and replication [137,150].…”

Section: Dsm Memorymentioning

confidence: 99%

“…Besides studies in CMP cache organizations [67,113,146], many hybrid caching schemes have been proposed to reduce the average memory access latency for CMPs [14,15,27,59,68,94,115,138,158,159].…”

Section: Cmp Caching Optimizations For Latency Reductionmentioning

confidence: 99%

“…Oi and Ranganathan [115] made the analogy between CMP caching and CC-NUMA memory organization, and evaluated the benefit of using part of the shared L2 cache as fix-sized victim caches. They discovered that aggressive replication (using large victim caches) can hurt performance, and for SPLASH2…”

Section: Shared Cache Based Proposalsmentioning

confidence: 99%

“…Pure private caches make efficient use of their portion of on-chip cache resources, leading to more local L2 hits (higher P LocalL2 ) as well as potentially more off-chip accesses (higher P M em ); a shared cache can reduce off-chip misses by storing data across the chip, but a local bank is only able to satisfy a fraction of total L1 misses (lower P LocalL2 ). Shared cache based hybrid schemes try to exploit data replication and migration to increase local L2 hit ratio (higher P LocalL2 and lower P RemoteL2 ), without significantly increasing off-chip accesses [15,27,94,115,158,159].…”

Section: Motivationmentioning

confidence: 99%

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Cooperative Caching for Chip Multiprocessors

Sohi

¹

,

Chang

²

33rd International Symposium on Computer Architecture (ISCA'06)

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Chip multiprocessor (CMP) systems have made the on-chip caches a critical resource shared among co-scheduled threads. Limited off-chip bandwidth, increasing on-chip wire delay, destructive inter-thread interference, and diverse workload characteristics pose key design challenges. To address these challenge, we propose CMP cooperative caching (CC), a unified framework to efficiently organize and manage on-chip cache resources. By forming a globally managed, shared cache using cooperative private caches. CC can effectively support two important caching applications: (1) reduction of average memory access latency and (2) isolation of destructive inter-thread interference.CC reduces the average memory access latency by balancing between cache latency and capacity optimizations. Based private caches, CC naturally exploits their access latency benefits. To improve the effective cache capacity, CC forms a "shared" cache using replication control and LRU-based global replacement policies. Via cooperation throttling, CC provides a spectrum of caching behaviors between the two extremes of private and shared caches, thus enabling dynamic adaptation to suit workload requirements. We show that CC can achieve a robust performance advantage over private and shared cache schemes across different processor, cache and memory configurations, and a wide selection of multithreaded and multiprogrammed workloads.To isolate inter-thread caching interference, we add a time-sharing aspect on top of spatial cache partitioning. Our approach uses Multiple Time-sharing Partitions (MTP) to simultaneously improve throughput and fairness while maintaining QoS over the longer term. Each MTP partition unfairly improves at least one thread's throughput, and partitions favoring different threads are scheduled in a cooperative, timesharing manner to either maintain fairness and QoS, or implement priority. We also integrate MTP with CC's LRU-based capacity sharing policy to combine their benefits. The integrated scheme-Cooperative Caching Partitioning (CCP)-divides the total execution epochs into those controlled by either MTP or the ii baseline CC policy, respectively, according to the fraction of threads that can benefit from each of them. Our simulation results show that for a wide range of multiprogrammed workloads, CCP can improve throughput, fairness and QoS for workloads suffering from destructive interference, while achieving the performance benefit of the baseline CC policy for other workloads.iii

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Cooperative Caching for Chip Multiprocessors

Chang¹,

Herrero²,

Canal³

et al. 2011

Cooperative Networking

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Chip multiprocessor (CMP) systems have made the on-chip caches a critical resource shared among co-scheduled threads. Limited off-chip bandwidth, increasing on-chip wire delay, destructive inter-thread interference, and diverse workload characteristics pose key design challenges. To address these challenge, we propose CMP cooperative caching (CC), a unified framework to efficiently organize and manage on-chip cache resources. By forming a globally managed, shared cache using cooperative private caches. CC can effectively support two important caching applications: (1) reduction of average memory access latency and (2) isolation of destructive inter-thread interference.CC reduces the average memory access latency by balancing between cache latency and capacity optimizations. Based private caches, CC naturally exploits their access latency benefits. To improve the effective cache capacity, CC forms a "shared" cache using replication control and LRU-based global replacement policies. Via cooperation throttling, CC provides a spectrum of caching behaviors between the two extremes of private and shared caches, thus enabling dynamic adaptation to suit workload requirements. We show that CC can achieve a robust performance advantage over private and shared cache schemes across different processor, cache and memory configurations, and a wide selection of multithreaded and multiprogrammed workloads.To isolate inter-thread caching interference, we add a time-sharing aspect on top of spatial cache partitioning. Our approach uses Multiple Time-sharing Partitions (MTP) to simultaneously improve throughput and fairness while maintaining QoS over the longer term. Each MTP partition unfairly improves at least one thread's throughput, and partitions favoring different threads are scheduled in a cooperative, timesharing manner to either maintain fairness and QoS, or implement priority. We also integrate MTP with CC's LRU-based capacity sharing policy to combine their benefits. The integrated scheme-Cooperative Caching Partitioning (CCP)-divides the total execution epochs into those controlled by either MTP or the ii baseline CC policy, respectively, according to the fraction of threads that can benefit from each of them. Our simulation results show that for a wide range of multiprogrammed workloads, CCP can improve throughput, fairness and QoS for workloads suffering from destructive interference, while achieving the performance benefit of the baseline CC policy for other workloads.iii

show abstract

Utilization of cache area in on-chip multiprocessor

Cited by 10 publications

References 6 publications

Victim Migration: Dynamically Adapting Between Private and Shared CMP Caches

Victim Migration: Dynamically Adapting Between Private and Shared CMP Caches

Cooperative Caching for Chip Multiprocessors

Cooperative Caching for Chip Multiprocessors

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