UTBB FDSOI transistors with dual STI for a multi-V&lt;inf&gt;t&lt;/inf&gt; strategy at 20nm node and below

Grenouillet, L.; Vinet, M.; Gimbert, J.; Giraud, B.; Noël, Jean-Philippe; Liu, Q.; Khare, Prasanna; Jaud, Marie-Anne; Tiec, Y. Le; Wacquez, R.; Levin, T. M.; Rivallin, P.; Holmes, Steven J.; Liu, S.; Chen, K. J.; Rozeau, O.; Scheiblin, P.; Mclellan, Erin; Malley, Matthew; Guilford, J.; Upham, A.; Johnson, Rob; Hargrove, M.; Hook, T.B.; Schmitz, Stefan; Mehta, S.; Kuss, J.; Loubet, N.; Teehan, S.; Terrizzi, M.; Ponoth, S.; Cheng, K.; Nagumo, T.; Khakifirooz, A.; Monsieur, F.; Kulkarni, P.; Conte, Rosa Ana; Demarest, J.; Faynot, O.; Kleemeier, W.; Luning, S.; Doris, B.

doi:10.1109/iedm.2012.6478974

Cited by 41 publications

(18 citation statements)

References 2 publications

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“…Ultra-thin body and BOX (UTBB) fully depleted silicon-oninsulator (FD-SOI) devices are one of the promising candidates for future CMOS technology nodes since they could offer excellent electrostatic integrity, high performance and low variability [1]. In addition, there are interesting potentialities that the usage of static and dynamic back plane (BP) biasing engineering in UTBB architecture has made available to exploit the multi-V T strategies with a planar implementation [2].…”

Section: Introductionmentioning

confidence: 99%

In depth characterization of electron transport in 14 nm FD-SOI CMOS devices

Shin

Shi

Mouis

et al. 2015

Solid-State Electronics

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Section: Introductionmentioning

confidence: 99%

In depth characterization of electron transport in 14 nm FD-SOI CMOS devices

Shin

Shi

Mouis

et al. 2015

Solid-State Electronics

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“…The explored range of channel length (L) values was selected accordingly, to fulfill the geometrical MR requirement [12]. Device fabrication details could be found in [1], [2], and [13]. Magnetotransport measurements were carried out using superconducting coils, which allow magnetic field variation between 0 and 11 T. Measurements were performed in a cryostat filled by helium where the temperature of the sample could be controlled.…”

Section: Experimental Details and Device Descriptionmentioning

confidence: 99%

Experimental and Theoretical Investigation of Magnetoresistance From Linear Regime to Saturation in 14-nm FD-SOI MOS Devices

Shin

Shi

Mouis

et al. 2015

IEEE Trans. Electron Devices

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The feasibility of geometric magnetoresistance (MR) measurement from linear to saturation operation regime is demonstrated in ultrathin body and BOX fully depleted siliconon-insulator devices from 14-nm technology node. Besides, we propose a new physical compact model for MOSFET drain current under high field transport, which reproduces experimental MR mobility from linear to saturation operation region and serves as the basis for a new extraction method of carrier saturation velocity. A benchmarking with state-of-the-art saturation velocity extraction methodologies is also conducted. Our saturation velocity results indicate that, for this technology, nonstationary transport prevails as manifested by an overshoot velocity behavior, still far from the ballistic limit.Index Terms-Magnetoresistance (MR), mobility, out-ofequilibrium transport, saturation regime, saturation velocity, ultrathin body and BOX (UTBB).

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“…We demonstrate a and VDDmin with respect to s by appropriately biasing the different transistors [12], and w 10T bitcells in this paper. The be separately contacted by architecture [13].…”

Section: Rnm Wm Icellmentioning

confidence: 99%

Circuit optimization of 4T, 6T, 8T, 10T SRAM bitcells in 28nm UTBB FD-SOI technology using back-gate bias control

Asthana

Kar

Jiménez

et al. 2013

2013 Proceedings of the ESSCIRC (ESSCIRC)

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SRAM bitcell optimization demonstrated in 28nm High-κ Metal Gate U Body and BOX) FD-SOI technology. The b biasing leads to forward or reverse bias of the been used to improve the bitcell electrical me 6T bitcell variants show a gain of 67% (25% 0.6V (1V), 45% reduction in write time at 0.6V in either write margin or static noise margin bitcell variants using back-gate bias have be compared for performance, power and stab back-gate biasing concept has been extended t bitcells and their simulation results are also pre Keywords-SRAM, UTBB FD-SOI, SNM, R I.

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UTBB FDSOI transistors with dual STI for a multi-V<inf>t</inf> strategy at 20nm node and below

Cited by 41 publications

References 2 publications

In depth characterization of electron transport in 14 nm FD-SOI CMOS devices

In depth characterization of electron transport in 14 nm FD-SOI CMOS devices

Experimental and Theoretical Investigation of Magnetoresistance From Linear Regime to Saturation in 14-nm FD-SOI MOS Devices

Circuit optimization of 4T, 6T, 8T, 10T SRAM bitcells in 28nm UTBB FD-SOI technology using back-gate bias control

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