Using partial reconfiguration and high-level models to accelerate FPGA design validation

22nd International Conference on Field Programmable Logic and Applications (FPL)

Luk

et al. 2012

Stencil computation is computationally intensive and required by many applications. This paper proposes an approach to exploit run-time reconfigurability of field-programmable accelerators for stencil computation. System throughput is optimized by partitioning, analysing and scheduling tasks in applications to remove idle functions. To evaluate the proposed approach, Reverse Time Migration (RTM), a high performance application, is developed. Our optimized runtime reconfigurable solution, which targets a Virtex-6 FPGA in a Maxeler MAX3424A system, can achieves an improved throughput of 102.8 GFlop/s, up to two orders of magnitude faster than the CPU reference designs, 1.59 times faster than the best published GPU and FPGA results, and 1.45 times faster than an optimized static implementation.

Section: Resultsmentioning

confidence: 99%

“…At design time, the dynamic property is used to improve floorplanning [2] and to accelerate design validation [3]. During run-time, applications with slowly varying inputs and various scenarios are dynamically optimised.…”

Section: Run-time Reconfigurationmentioning

confidence: 99%

Exploiting run-time reconfiguration in stencil computation

22nd International Conference on Field Programmable Logic and Applications (FPL)

Luk

et al. 2012

“…During design time, run-time reconfiguration can be used to accelerate design validation [2]. During run time, designs with slowly varying inputs can benefit from run-time reconfiguration.…”

Section: Related Workmentioning

confidence: 99%

Automating Elimination of Idle Functions by Run-Time Reconfiguration

Chau

2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines

et al. 2013

A design approach is proposed to automatically identify and exploit run-time reconfiguration opportunities while optimising resource utilisation. We introduce Reconfiguration Data Flow Graph, a hierarchical graph structure enabling reconfigurable designs to be synthesised in three steps: function analysis, configuration organisation, and run-time solution generation. Three applications, based on barrier option pricing, particle filter, and reverse time migration are used in evaluating the proposed approach. The run-time solutions approximate the theoretical performance by eliminating idle functions, and are 1.31 to 2.19 times faster than optimised static designs. FPGA designs developed with the proposed approach are up to 28.8 times faster than optimised CPU reference designs and 1.55 times faster than optimised GPU designs.

“…At design time, efficiency of floorplanning [Singhal and Bozorgzadeh 2006] and performance of design validation [Iskander et al 2010] are improved. During runtime, slowly changing applications are optimised with runtime reconfiguration.…”

Section: Related Workmentioning

confidence: 99%

A Self-Aware Tuning and Self-Aware Evaluation Method for Finite-Difference Applications in Reconfigurable Systems

ACM Trans. Reconfigurable Technol. Syst.

Luk

et al. 2014

Finite-difference methods are computationally intensive and required by many applications. Parameters of a finite-difference algorithm, such as grid size, can be varied to generate design space which contains algorithm instances with different constant coefficients. An algorithm instance with specific coefficients can either be mapped into general operators to construct static designs, or be implemented as constant-specific operators to form dynamic designs, which require runtime reconfiguration to update algorithm coefficients. This article proposes a tuning method to explore the design space to optimise both the static and the dynamic designs, and an evaluation method to select the design with maximum overall throughput, based on algorithm characteristics, design properties, available resources and runtime data size. For benchmark applications option pricing and Reverse-Time Migration (RTM), over 50% reduction in resource consumption has been achieved for both static designs and dynamic designs, while meeting precision requirements. For a single hardware implementation, the RTM design optimised with the proposed approach is expected to run 1.8 times faster than the best published design. The tuned static designs run thousands of times faster than the dynamic designs for algorithms with small data size, while the tuned dynamic designs achieve up to 5.9 times speedup over the corresponding static designs for large-scale finite-difference algorithms. . 2014. A self-aware tuning and self-aware evaluation method for finite-difference applications in reconfigurable systems.