Using operating point-dependent degradation and g<inf>m</inf>/I<inf>D</inf> method for aging-aware design

Abstract

Effects like NBTI and HCI are degrading the characteristics of analog circuits. Available countermeasures to maintain system performances often include the use of optimizers or other external tools to size devices appropriately, which give no insight in relations between degradation and circuit parameters for the designer. This paper proposes an extension of the g m/ID sizing method by considering aged transistor parameters for fresh circuit design. A possible usage scenario for this investigation is given by optimizing a simple circuit towards higher reliability. The degradation in amplification of a common source amplifier is reduced by 19 % for a full time operation of 10 years.

Charge-based stochastic aging analysis of CMOS circuits

“…In [3] an approached using analog behavioral aging models and RelXpert is presented. In [4] a method for an aging-aware design based on the gm/Id work flow investigating the impact of aging on circuit level is introduced.…”

An aging-aware transistor sizing tool regarding BTI and HCD degradation modes

“…In order to design analog circuits with respect to aging, the impact of degradation on transistor parameter needs to be available in advance, such that changes in system characteristics may be determined during design phase, without any further SPICE simulations. The propesed GMID-Tool for an aging-aware design flow does not only exploit recent advances in operating point-dependent degradation [10], but also natively provides aged representations of circuit performance characteristics.…”