Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains

Wu, Shianling; Wang, Laung-Terng; Wen, Xiaoqing; Jiang, Zhigang; Tan, Lang; Hu, Yu; Jone, Wen-Ben; Hsiao, Michael S.; Li, James Chien-Mo; Huang, Jiun-Lang; Lu, Yu

doi:10.1109/tcad.2010.2092510

Cited by 5 publications

(2 citation statements)

References 16 publications

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“…The nodes in the design must control and observe and control and observe the test vectors should send through scan chains. This testing will happen in three phases first load, second shift then capture [8], as each phase depends on the clock edge, clock cycles play a significant role in the timing. In the shift to test the functionality, mainly against any stuck-at faults [9], [10] of the designed chip, the sequential devices will be stitched in the chain order, and the test pattern to detect the fault is applied in the series.…”

Section: Introductionmentioning

confidence: 99%

An effective way to generate the shift timing constraints and sanity checks

Afridi¹,

Shylashree²,

Tunga

et al. 2023

IJEECS

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Design for testability (DFT) is a technique, which facilitates a design to become testable after fabrication. As the technology node is shrinking, complexity of the system-on-chip (SoC) becomes high and inserting DFT and verifying its timing becomes complex. For these complex SoC, generating DFT timing constraints becomes difficult in shift mode and the time required for the generation of these timing constraints is also more. A new methodology proposed to overcome these issues. The main objective of this work is to propose the flow for generating DFT timing constraints for the complex SoC in shift mode, by dividing the design blocks into scan blocks and non-scan blocks. To target the whole design without getting all paths reported, relaxation of the setup, and hold time for non-scan blocks plays crucial role. If not, the time taken to generate DFT timing constraints would be more. Implemented methodology of this paper includes design setup, timing exceptions, and synopsys design constraints (SDC) generation for DFT timing. Design setup consists of all pre-requisites for design such as netlists, timing libraries, and exceptions. Synopsys primetime (PT Shell) is used for all the timing-related checks. Compared to conventional methods, the proposed flow reduces the overall time by 40% to generate constraints.

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Section: Introductionmentioning

confidence: 99%

An effective way to generate the shift timing constraints and sanity checks

Afridi¹,

Shylashree²,

Tunga

et al. 2023

IJEECS

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show abstract

“…This was achieved as one-hot clocking will always be utilized after staggered clocking, leading for no loss in fault report in the hybrid testing. This approach failed as the parameters of the previously existing approach did not match with the proposed approach, as the existing work had the potential to be applied for all synchronous clock domains [4]. In hybrid ATPG switches alternative approach was proposed, from the staggered type to one-hot type post determined proportion of errors have been processed.…”

mentioning

confidence: 99%

Fault simulation for design for testability inserted designs

Gowda

Jamuna²

2023

IJEECS

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<p>Systematic design for testability (DFT) is a technique to enhance the testability of design so that it is further organized and self-regulating. The objective of systematic DFT is to enhance a circuit's operability and evidence. This can be performed in a variety of ways. The scan pattern method is the extremely predominant, and it modifies the design's internal sequential circuitry. In this manuscript, frequently used industry standard functional register-transfer level (RTL) designs are chosen. Structured DFT approach is adopted to do scan insertion and automatic test pattern generation (ATPG) to enhance the testability. Proposed methodology provides the controllability and observability for the clocks and reset used in chosen RTL designs by eliminating S rule and D rule violations by adding test logic. Also able to insert stuck at faults and achieve fault coverage of 97.78% and test coverage of 99.26% for DFT architecture for Wallace tree multiplier design, and found different classes of faults as testable and untestable faults and also performed fault simulation for the intended designs to detect fault from the created deterministic patterns.</p>

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Improved test methodology for multi-clock domain SoC ATPG testing

Ooi

Ang

2013

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013)

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Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains

Cited by 5 publications

References 16 publications

An effective way to generate the shift timing constraints and sanity checks

An effective way to generate the shift timing constraints and sanity checks

Fault simulation for design for testability inserted designs

Improved test methodology for multi-clock domain SoC ATPG testing

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