Using Domain Partitioning in Wrapper Design for IP Cores Under Power Constraints

Yu, Thomas Edison; Yoneda, Tomokazu; Zhao, Danella; Fujiwara, Hideo

doi:10.1109/vts.2007.86

Cited by 5 publications

(2 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The recent IEEE 1500 standard addresses wrapper design, but it leaves TAM optimization to the system integrator. Therefore, TAM optimization and test scheduling at the SOC level has been an active area of research in recent years [2]- [5]. Prior work has been limited to traditional two-dimensional (2D) integrated circuits (ICs), which is the widely used technology today for IC manufacturing.…”

Section: Introductionmentioning

confidence: 99%

Test-access mechanism optimization for core-based three-dimensional SOCs

Chen

Chakrabarty

et al. 2010

Microelectronics Journal

View full text Add to dashboard Cite

Abstract-Test-access mechanisms (TAMs) and test wrappers (e.g., the IEEE Standard 1500 wrapper) facilitate the modular testing of embedded cores in a core-based system-on-chip (SOC). Such a modular testing approach can also be used for emerging three-dimensional integrated circuits based on through-silicon vias (TSVs). Core-based SOCs based on 3D IC technology are being advocated as a means to continue technology scaling and overcome interconnect-related bottlenecks. We present an optimization technique for minimizing the test time for 3D core-based SOCs under constraints on the number of TSVs and the TAM bitwidth. The proposed optimization method is based on a combination of integer linear programming, LP-relaxation, and randomized rounding. Simulation results are presented for the ITC 02 SOC Test Benchmarks and the test times are compared to that obtained when methods developed earlier for two-dimensional ICs are applied to 3D ICs.

show abstract

Section: Introductionmentioning

confidence: 99%

Test-access mechanism optimization for core-based three-dimensional SOCs

Chen

Chakrabarty

et al. 2010

Microelectronics Journal

View full text Add to dashboard Cite

show abstract

“…Therefore, efficient heuristic techniques have been developed for SoC test planning and TAM optimization [Goel and Marinissen 2002;Gonciari et al 2003;Huang et al 2002;Iyengar et al 2003b;Larsson and Peng 2002;Zhao and Upadhyaya 2003;Yoneda et al 2007;Yu et al 2007;Xu and Nicolici 2005]. However, it is assumed in all these methods that at any instant in time, the ATE provides test stimuli to the SoC at a single data rate.…”

Section: Introductionmentioning

confidence: 99%

Power-aware SoC test planning for effective utilization of port-scalable testers

Sehgal

Bahukudumbi

Chakrabarty

2008

ACM Trans. Des. Autom. Electron. Syst.

View full text Add to dashboard Cite

Many system-on-chip (SoC) integrated circuits contain embedded cores with different scan frequencies. To better meet the test requirements for such heterogeneous SoCs, leading tester companies have recently introduced port-scalable testers, which can simultaneously drive groups of channels at different data rates. However, the number of tester channels available for scan testing is limited; therefore, a higher shift frequency can increase the test time for a core if the resulting test access architecture reduces the bit-width used to access it. We present a scalable test planning technique that exploits port scalability of testers to reduce SoC test time. We compare the proposed heuristic optimization method to two baseline methods based on prior works that use a single scan data rate for all embedded cores. We also propose a power-aware test planning technique to effectively utilize port-scalable testers under constraints of test power consumption. Experimental results are presented for power-aware test scheduling to illustrate the impact of power constraints on overall test time.

show abstract