Using Data Compression in Automatic Test Equipment for System-on-Chip Testing

“…A technique for less storage on ATE environment for compression has been presented in [15] in which a maximal set of reusable segments in the test data is found and then compressed. The practical problems of once existing test data compression technique is addressed in [16] and to reduce the ATE storage requirement, a columnwise processing of test data is proposed in [16].…”

Section: B Reordering Of Test Vectorsmentioning

confidence: 99%

Hamming Distance Based 2-D Reordering with Power Efficient Don't Care Bit Filling: Optimizing the test data compression method

Mehta

Devashrayee

Dasgupta

2010

2010 International Symposium on System on Chip

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This paper presents a method to compress partially specified test data for a given SoC in Automatic Test Equipment (ATE). A method "Hamming Distance Based 2-Dimensional Reordering with Power Efficient Don't Care Bit Filling" is presented for compression of test data in which two dimensional i.e. row and columnwise test vector reordering and power optimized don't care bit filling method is applied. The advantage of the approach is a good compression with very low test power achieved without adding area overhead. The advantages are shown by experimental results with ISCAS benchmark circuits.

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“…Since correlations between test vectors are usually high, due to the circuit structure dependency, test vector correlation is exploited to minimize the bit flips or the replacement words between consequent test patterns [7,8,9,10,11]. Furthermore, don't care bits in test patterns can also be exploited to further improve compression efficiency.…”

Section: Correlation-relatedmentioning

confidence: 99%

Adaptive Encoding Scheme for Test Volume/Time Reduction in SoC Scan Testing

Lin

Lee

Chen

2005

14th Asian Test Symposium (ATS'05)

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Scan test for SoC has now suffered large data volume and test application time. In this paper, we propose and demonstrate an Adaptive Encoding scheme to reduce the test volume and test time for SoC scan test. The scheme, instead of handling test data themselves, encodes them in "packets" according to difference bits of two consecutive test patterns. A decoder machine is designed to decode the compressed data and a repeat filling mechanism from the ATE is adopted to eliminate the synchronization problem. It supports variable block size and is flexible in encoding multi-core test patterns; therefore, the proposed method is effective in SoC scan test. Experimental results show that on average the scheme achieves 73% reduction in test data and more than 16 times of speedup in test application time.

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Using Data Compression in Automatic Test Equipment for System-on-Chip Testing

Cited by 13 publications

References 11 publications

Master-slave based test cost reduction method for DNN accelerators

Master-slave based test cost reduction method for DNN accelerators

Hamming Distance Based 2-D Reordering with Power Efficient Don't Care Bit Filling: Optimizing the test data compression method

Adaptive Encoding Scheme for Test Volume/Time Reduction in SoC Scan Testing

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