User- and process-driven dynamic voltage and frequency scaling

Lin, Bin; Mallik, Arindam; Dinda, Peter A.; Memik, Gokhan; Dick, Robert P.

doi:10.1109/ispass.2009.4919634

Cited by 27 publications

(19 citation statements)

References 33 publications

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“…Several teams have examined the combination of processor power variation and DVFS at processor granularity [14] (for the Pentium M architecture) and at the granularity of individual cores [19], [10] (on the AMD Opteron architecture), as well as on more exotic architectures [8], [6]. Herbert et al [9] took the next step by combining DVFS with work shifting to prioritize use of the most-efficient cores.…”

Section: Related Workmentioning

confidence: 99%

Beyond DVFS: A First Look at Performance under a Hardware-Enforced Power Bound

Rountree

Ahn

Supinski

et al. 2012

2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops &Amp; PhD Forum

142

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Abstract-Dynamic Voltage Frequency Scaling (DVFS) has been the tool of choice for balancing power and performance in high-performance computing (HPC). With the introduction of Intel's Sandy Bridge family of processors, researchers now have a far more attractive option: user-specified, dynamic, hardware-enforced processor power bounds. In this paper we provide a first look at this technology in the HPC environment and detail both the opportunities and potential pitfalls of using this technique to control processor power.As part of this evaluation we measure power and performance for single-processor instances of several of the NAS Parallel Benchmarks. Additionally, we focus on the behavior of a single benchmark, MG, under several different power bounds. We quantify the well-known manufacturing variation in processor power efficiency and show that, in the absence of a power bound, this variation has no correlation to performance. We then show that execution under a power bound translates this variation in efficiency into variation in performance.

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Section: Related Workmentioning

confidence: 99%

Beyond DVFS: A First Look at Performance under a Hardware-Enforced Power Bound

Rountree

Ahn

Supinski

et al. 2012

2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops &Amp; PhD Forum

142

View full text Add to dashboard Cite

show abstract

“…A typical open-loop AVS system utilizes a pre-characterized lookup table (LUT) to find the corresponding minimum supply voltage for a given chip frequency target [14] [5]. Since the open-loop technique does not have a feedback mechanism, the LUT is heavily guardbanded to ensure reliable system operation.…”

Section: Avs Techniques Can Be Classified As Either Open-or Closed-loopmentioning

confidence: 99%

“…To recover excess margin allocated for process variation, many adaptive voltage scaling (AVS) techniques have been proposed [5] [9] [14] [16] [17].…”

Section: Introductionmentioning

confidence: 99%

Tunable sensors for process-aware voltage scaling

Chan

Kahng

2012

Proceedings of the International Conference on Computer-Aided Design

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Abstract-VLSI circuits usually allocate excess margin to account for worst-case process variation. Since most chips are fabricated at process conditions better than the worst-case corner, adaptive voltage scaling (AVS) is commonly used to reduce power consumption whenever possible. A typical AVS setup relies on a performance monitor that replicates critical paths of the circuit to guide voltage scaling. However, it is difficult to define appropriate critical paths for an SoC which has multiple operating modes and IPs. In this paper, we propose a different methodology for AVS which matches the voltage scaling characteristics of a circuit rather than the delays of critical paths. This fundamental change in monitoring strategy simplifies the monitoring circuitry as well as the calibration flow of conventional monitoring methods. To enable the proposed methodology, we study voltage scaling characteristics of digital circuits. Based on our analyses, we develop design guidelines as well as design monitoring circuits which have tunable voltage scaling characteristics. Our experimental results show that this methodology can be used for AVS with a simplified calibration flow.

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“…Our work takes place in the context of the Empathic Systems Project [5], which has generally found that there is a high degree of variation in user satisfaction with any given operating point in a system, and that variation can be exploited by autonomic control that tailors for the individual user. Of relevance to this paper, we have demonstrated a range of user-driven systems for power management [17,18,9,11]. However, none of these studies analyze display power management.…”

Section: Related Workmentioning

confidence: 99%

Display power management policies in practice

Tarzia

Dinda

Dick

et al. 2010

Proceedings of the 7th International Conference on Autonomic Computing

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We present the first study of the real-world behavior of display power management (DPM) policies. DPM policies control the mechanism of powering on and off the displayturning off the display typically reduces total system power by ∼31%. The most widely used DPM policy, human interface device (HID) timeout, powers off the display after a user-configurable period of human interface device inactivity, and powers it back on in response to activity. To increase energy savings, we also consider an alternative policy, user presence detection, that uses sonar sensing to power off the display when user absence is detected. Our study captures how these DPM policies work "in the wild", both in terms of energy savings and the user irritation. We also determine the maximum energy saving opportunity for any DPM policy, based on measured behavior. Our study, based on a 3,738 hours of computer usage by 181 volunteers with different machines, reveals several surprising results. User idle periods follow power law distributions with little temporal correlation. The maximum possible reduction in energy used for the display is 81%, while the HID timeout policy manages to reduce this energy by 51%. Many users have already customized the HID timeout policy on their machines, resulting in a high variation of timeout values, and surprisingly low levels of user irritation. However, the 44% of users that have not customized HID timeouts experience more irritation. The proposed user presence detection policy, when effective, further reduces display energy consumption by 10% when combined with the HID timeout policy. 40% of the 2,869 machines tested can effectively generate and record ultrasound for sonar.

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User- and process-driven dynamic voltage and frequency scaling

Abstract: Abstract

Cited by 27 publications

References 33 publications

Beyond DVFS: A First Look at Performance under a Hardware-Enforced Power Bound

Beyond DVFS: A First Look at Performance under a Hardware-Enforced Power Bound

Tunable sensors for process-aware voltage scaling

Display power management policies in practice

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