Use of CMOS Technology in Wave Pipelining

Klass, F.; Mulder, J.

doi:10.1109/icvd.1992.658067

Cited by 16 publications

(3 citation statements)

References 5 publications

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“…The study reported in [10] shows that under proper design constraints, the overall delay variation of a conventional static CMOS circuit is relatively small, despite substantial variations of a single CMOS gate. For a 4-bit adder slice, the worst-case delay variation is about 10%.…”

Section: Cmos Wave Pipeliningmentioning

confidence: 98%

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Fast multiplication in VLSI using wave pipelining techniques

Klass

Flynn

Goor

1994

Journal of VLSI Signal Processing

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Abstract. Wave pipelining is a design methodology that can increase the clock frequency of digital systems. Also known as maximum-rate pipelining, it has long been considered a technique for approaching the physical speed limit of a digital circuit. Unlike conventional pipelining, wave pipelining does not require internal clocked elements to increase throughput. The synchronization of internal computations is achieved by balancing inherent RC delays of combinational logic elements, thus allowing circuits to be pipelined at a very fine-grain level. In this article, we describe the design of a 16 x 16 wave-pipelined multiplier using a 1.0 ~m CMOS process. The multiplier is designed using a conventional static CMOS technology. Simulation results show a speedup of about 7x over a nonpipeline implementation.

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Section: Cmos Wave Pipeliningmentioning

confidence: 98%

“…We have adopted the design constraints reported in [10] in order to minimize delay variations for CMOS. Therefore, only 2-input NAND gates and inverters are used for the synthesis of our wave-pipelined multiplier.…”

Section: Cmos Wave Pipeliningmentioning

confidence: 99%

Fast multiplication in VLSI using wave pipelining techniques

Klass

Flynn

Goor

1994

Journal of VLSI Signal Processing

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“…The effect is more pronounced in the case of complex gates having varying number of stacked transistors in different parallel paths. Klass and Mulder [7] have proposed to use a modified two-input NAND gate in static CMOS as the basic building block of wave pipelined digital systems. Gray et al [8] propose to use cross coupled two-input pseudo-nMOS NAND gates.…”

Section: Selection Of the Logic Stylementioning

confidence: 99%

Design and realization of high-performance wave-pipelined 8/spl times/8 b multiplier in CMOS technology

Ghosh

Nandy

1995

IEEE Trans. VLSI Syst.

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Wave pipelining is a design technique for increasing the throughput of a digital circuit or system without introducing pipelining registers between adjacent combinational logic blocks in the circuitfsystem. However, this requires balancing of the delays along all the paths from the input to the output which comes the way of its implementation. Static CMOS is inherently susceptible to delay variation with input data, and hence, receives a low priority for wave pipelined digital design. On the other hand, ECL and CML, which are amenable to wave pipelining [l], lack the compactness and low power attributes of CMOS. In this paper we attempt to exploit wave pipelining in CMOS technology. We use a single generic building block in Normal Process Complementary Pass Transistor Logic (NPCPL) [2], modeled after CPL [3], to achieve equal delay along all the propagation paths in the logic structure. An 8 x 8 b multiplier is designed using this logic in a 0 . 8~ technology. The carrysave multiplier architecture is modified suitably to support wave pipelining, viz., the logic depth of all the paths are made identical. The 1 mm x 0.6 mm multiplier core supports a throughput of 400 MHz and dissipates a total power of 0.6 W. We develop simple enhancements to the NPCPL building blocks that allow the multiplier to sustain throughputs in excess of 600 MHz. The methodology can be extended to introduce wave pipelining in other circuits as well.Zndex Terms-High performance multiplier macrocell, high throughput arithmetic unit, VLSI multipliers, wave pipelined multiplier, wave pipelining in CMOS technology.

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A maximum time difference pipelined arithmetic unit based on CMOS gate array

Tang

Xia

1995

J. of Comput. Sci. & Technol.

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Use of CMOS Technology in Wave Pipelining

Cited by 16 publications

References 5 publications

Fast multiplication in VLSI using wave pipelining techniques

Fast multiplication in VLSI using wave pipelining techniques

Design and realization of high-performance wave-pipelined 8/spl times/8 b multiplier in CMOS technology

A maximum time difference pipelined arithmetic unit based on CMOS gate array

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