UnSync-CMP: Multicore CMP Architecture for Energy-Efficient Soft-Error Reliability

Jeyapaul, Reiley; Hong, Fei; Rhisheekesan, Abhishek; Shrivastava, Aviral; Lee, Kyoungwoo

doi:10.1109/tpds.2013.14

Cited by 10 publications

(6 citation statements)

References 18 publications

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“…Jeyapaul et al [40] proposed UnSync-CMP, a customizable and redundant Chip Multiprocessor (CMP). The platform uses redundancy to handle cache soft errors.…”

Section: Related Workmentioning

confidence: 99%

Energy Optimization for Large-Scale 3D Manycores in the Dark-Silicon Era

et al. 2019

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In this paper, we study the impact of the idle/dynamic power consumption ratio on the effectiveness of a multi-V dd /frequency manycore design. We propose a new tool called LVSiM (a Low-Power and Variation-Aware Manycore Simulator) to carry out the experiments. It is a novel manycore simulator targeted towards low-power optimization methods including within-die process and workload variations. LVSiM provides a holistic platform for multi-V dd /frequency voltage island analysis, optimization, and design. It provides a tool for the early design exploration stage to analyze large-scale manycores with a given number of cores on 3D-stacked layers, network-on-chip communication busses, technology parameters, voltage and frequency values, and power grid parameters, using a variety of different optimization methods. LVSiM has been calibrated with Sniper/McPAT at a nominal frequency, and then the energy-delay-product (EDP) numbers were compared after frequency scaling. The average error is shown to be 10% after frequency scaling, which is sufficient for our purposes. The experiments in this work are carried out for different Idle/Dynamic ratios considering 1260 benchmarks with task sizes ranging from 4000 to 16 000 executing on 3200 cores. The best configurations are shown to produce on average 20.7% to 24.6% EDP savings compared to the nominal configuration. Traditional scheduling methods are used in the nominal configuration with the unused cores switched off. In addition, we show that, as the Idle/Dynamic ratio increases, the multi-V dd /frequency approach becomes less effective. In the case of a high Idle/Dynamic ratio, the minimum EDP can be achieved through switching off unused cores as opposed to using a multi-V dd /frequency approach. This conclusion is important, especially in the dark-silicon era, where switching cores on and/or off as needed is a common practice.

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“…Jeyapaul et al [40] proposed UnSync-CMP, a customizable and redundant Chip Multiprocessor (CMP). The platform uses redundancy to handle cache soft errors.…”

Section: Related Workmentioning

confidence: 99%

Energy Optimization for Large-Scale 3D Manycores in the Dark-Silicon Era

et al. 2019

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“…Some works, e.g. [35], [36], [37] have proposed multi-core architectures that exploit redundancy at different levels of abstraction to target low-energy consumption and reliability. [35] has proposed an adaptive multicore architecture that selectively adjusts pipeline-level redundancy to satisfy reliability target with low energy consumption.…”

Section: Related Workmentioning

confidence: 99%

“…[35] has proposed an adaptive multicore architecture that selectively adjusts pipeline-level redundancy to satisfy reliability target with low energy consumption. [36] has proposed a customizable chip-level redundancy technique for multi-core systems that utilizes power efficient hardware fault-detection mechanisms along with forward recovery to reduce overheads in case of fault-free executions. [37] has considered the effects of DVS on the soft error rate and proposed a flexible dual modular redundancy (DMR) mechanism that selectively enables per-core DMR to increase reliability.…”

Section: Related Workmentioning

confidence: 99%

Two-Phase Low-Energy N-Modular Redundancy for Hard Real-Time Multi-Core Systems

Salehi

Ejlali

Al-Hashimi

2016

IEEE Trans. Parallel Distrib. Syst.

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Abstract-This paper proposes an N-modular redundancy (NMR) technique with low energy-overhead for hard real-time multicore systems. NMR is well-suited for multi-core platforms as they provide multiple processing units and low-overhead communication for voting. However, it can impose considerable energy overhead and hence its energy overhead must be controlled, which is the primary consideration of this paper. For this purpose the system operation can be divided into two phases: indispensable phase and on-demand phase. In the indispensable phase only half-plus-one copies for each task are executed. When no fault occurs during this phase, the results must be identical and hence the remaining copies are not required. Otherwise, the remaining copies must be executed in the on-demand phase to perform a complete majority voting. In this paper, for such a two-phase NMR, an energy-management technique is developed where two new concepts have been considered: i) Block-partitioned scheduling that enables parallel task execution during on-demand phase, thereby leaving more slack for energy saving, ii) Pseudo-dynamic slack, that results when a task has no faulty execution during the indispensable phase and hence the time which is reserved for its copies in the on-demand phase is reclaimed for energy saving. The energymanagement technique has an off-line part that manages static and pseudo-dynamic slacks at design time and an online part that mainly manages dynamic slacks at run-time. Experimental results show that the proposed NMR technique provides up to 29% energy saving and is 6 orders of magnitude higher reliable as compared to a recent previous work.

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“…For example, the recent work of Upasani et al [2014a] keeps two copies of the register file and the register allocation table (RAT) to achieve low performance overhead. Jeyapaul et al [2014] explore multicore CMP architecture to recover from soft errors with an efficiently modified cache structure. However, they rely on only parity checking to sequential logic for detecting a soft error; that is, combinational logic is still vulnerable to the soft errors and thus they may generate SDC.…”

Section: Soft Error Recoverymentioning

confidence: 99%

Compiler-Directed Soft Error Detection and Recovery to Avoid DUE and SDC via Tail-DMR

Liu

Jung

Lee

et al. 2016

ACM Trans. Embed. Comput. Syst.

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This article presents Clover, a compiler-directed soft error detection and recovery scheme for lightweight soft error resilience. The compiler carefully generates soft-error-tolerant code based on idempotent processing without explicit checkpoints. During program execution, Clover relies on a small number of acoustic wave detectors deployed in the processor to identify soft errors by sensing the wave made by a particle strike. To cope with DUEs (detected unrecoverable errors) caused by the sensing latency of error detection, Clover leverages a novel selective instruction duplication technique called tail-DMR (dual modular redundancy) that provides a region-level error containment. Once a soft error is detected by either the sensors or the tail-DMR, Clover takes care of the error as in the case of exception handling. To recover from the error, Clover simply redirects program control to the beginning of the code region where the error is detected. The experimental results demonstrate that the average runtime overhead is only 26%, which is a 75% reduction compared to that of the state-of-the-art soft error resilience technique. In addition, this article evaluates an alternative technique called tail-wait, comparing it to Clover. According to the evaluation with the different processor configurations and the various error detection latencies, Clover turns out to be a superior technique, achieving 1.06 to 3.49× speedup over the tail-wait.

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UnSync-CMP: Multicore CMP Architecture for Energy-Efficient Soft-Error Reliability

Cited by 10 publications

References 18 publications

Energy Optimization for Large-Scale 3D Manycores in the Dark-Silicon Era

Energy Optimization for Large-Scale 3D Manycores in the Dark-Silicon Era

Two-Phase Low-Energy N-Modular Redundancy for Hard Real-Time Multi-Core Systems

Compiler-Directed Soft Error Detection and Recovery to Avoid DUE and SDC via Tail-DMR

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