UnSync: A Soft Error Resilient Redundant Multicore Architecture

Abstract

Abstract-Reducing device dimensions, increasing transistor densities, and smaller timing windows, expose the vulnerability of processors to soft errors induced by charge carrying particles. Since these factors are only consequences of the inevitable advancement in processor technology, the industry has been forced to improve reliability on general purpose Chip Multiprocessors (CMPs). With the availability of increased hardware resources, redundancy based techniques are the most promising methods to eradicate soft error failures in CMP systems. In this work, we propose a novel redundant CMP architecture (UnSync) that utilizes hardware based detection mechanisms (most of which are readily available in the processor), to reduce overheads during error free executions. In the presence of errors (which are infrequent), the always forward execution enabled recovery mechanism provides for resilience in the system. We design a detailed RTL model of our UnSync architecture and perform hardware synthesis to compare the hardware (power/area) overheads incurred. We compare the same with those of the Reunion technique, a state-of-the-art redundant multi-core architecture. We also perform cycle-accurate simulations over a wide range of SPEC2000, and MiBench benchmarks to evaluate the performance efficiency achieved over that of the Reunion architecture. Experimental results show that, our UnSync architecture reduces power consumption by 34.5% and improves performance by up to 20% with 13.3% less area overhead, when compared to Reunion architecture for the same level of reliability achieved.

Modelling and mitigation of soft-errors in CMOS processors

“…Second, the overhead of each processor core will contribute to the overall overhead of the entire multi-core system. As a result, recent research has suggested that the problem of soft-error resilience in multi-core systems needs to be approached from an orthogonal perspective [Jey11]; this means the approach should consider redundancy of different resources during the soft-error mitigation procedure.…”

“…Another state-of-the-art method has been proposed in [Jey11]. It is a promising method which is called Unsync.…”

“…In any case, there is no need to exchange the status between two processor cores. This feature is beneficiary as compared to Unsync [Jey11] in which the correct status of a core should be copied from the unaffected core to the erroneous one.…”

“…Multi-core architectures remain the main architecture of computer systems for the upcoming years because they provide a solution to continue enhancing the performance, while the increase in power consumption is still manageable. As a result, multi-core architectures have become very popular recently in the computer architecture community [Jey11], e.g. the Intel core 2 duo, Intel core i7, AMD Opteron and IBM Cell processor.…”

“…Investigation of the logged data showed that the failure was induced by toggling the value of one of the flip-flops; it turned out it was most probably caused by the strike of neutron particles originating from cosmic radiation [Lyo00]. That crash happened only once in the life time of that Sun server; however studies show that if the technology of implementation is less than 90nm, the soft-error rate at the end-point server can reach the rate of once per 170 hours [Jey11]. With the trends of shrinking technology and reduction of power supply, advanced digital systems can experience a failure induced by soft-errors at a rate of once per 24 hours [Kay00].…”