Unpinning the GaAs Fermi level with thin heavily doped silicon overlayers

Wood, J.

doi:10.1109/16.43804

Cited by 21 publications

(6 citation statements)

References 9 publications

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“…[12][13][14] Pseudomorphic silicon cap layer deposited onto GaAs was reported to unpin the surface Fermi energy 13,15 and reduce the density of tunneling-related traps. [12][13][14] Pseudomorphic silicon cap layer deposited onto GaAs was reported to unpin the surface Fermi energy 13,15 and reduce the density of tunneling-related traps.…”

Section: Introductionmentioning

confidence: 99%

Gate quality Si3N4 prepared by low temperature remote plasma enhanced chemical vapor deposition for III–V semiconductor-based metal–insulator–semiconductor devices

Park¹,

Tao²,

Li³

et al. 1996

Journal of Vacuum Science &Amp; Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena

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Radiation effects on metal-insulator-semiconductor diode energetic ion detectors J. Vac. Sci. Technol. B 6, 513 (1988); 10.1116/1.584061 III-V compound semiconductor insulated gate field effect transistors AIP Conf.We report the properties of silicon nitride films deposited by the electron cyclotron resonance remote plasma enhanced chemical vapor deposition method on Si substrates using SiH 4 and N 2 . The effects of nitrogen/silane gas ratio ͑RϭN 2 /SiH 4 ͒, electron cyclotron resonance power, substrate temperature, and H on growth, refractive index, chemical composition, and etch rate were investigated. Nominally stoichiometric Si 3 N 4 films were obtained with a refractive index of 1.9ϳ2.0 at a wavelength of 632.8 nm. The etch rate of the films in a buffered HF solution ͑7:1͒ was low ͑ϳ0.7 nm/min͒ and increased with increasing H 2 gas flow rate and decreasing substrate temperature during deposition. Fourier transform infrared spectroscopy and high temperature thermal evolution experiments showed very small amounts of H in the films. A leakage current less than 100 pA/cm 2 at a field of 2 MV/cm, a resistivity of Ͼ4ϫ10 17 ⍀ cm, and breakdown strengths of 6 -11 MV/cm at a current density of 1 A/cm 2 were observed. These properties are comparable to those of Si 3 N 4 prepared by conventional high temperature ͑700°C͒ chemical vapor deposition. The performance of GaAs-based field-effect-transistors in switching and power applications can be enhanced substantially by employing a metal-insulator-semiconductor structure. By taking advantage of an in situ process approach, insulator-GaAs structures were successfully gated with excellent interfacial properties.

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Section: Introductionmentioning

confidence: 99%

Gate quality Si3N4 prepared by low temperature remote plasma enhanced chemical vapor deposition for III–V semiconductor-based metal–insulator–semiconductor devices

Park¹,

Tao²,

Li³

et al. 1996

Journal of Vacuum Science &Amp; Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena

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“…Unfortunately, III-V/oxide interfaces are not quite as robust as the Si/SiO 2 one and most of them present rather high densities of interface states. One of the key problems in developing inversion-mode MISFETs is the near midgap Fermi level pinning associated with the high density of states present at the high-κ/III-V interface [66][67][68][69]. The origin of these interface states has been heavily debated on in the past [70] but there are clear indications that a strong relationship exists with native antisite point defects (As Ga or Ga As ) [69], as also evidenced by scanning tunneling microscopy data [71,72].…”

Section: Passivation Of the Gaas Surfacementioning

confidence: 99%

Shaping the future of nanoelectronics beyond the Si roadmap with new materials and devices

et al. 2010

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The use of high mobility channel materials such as Ge and III/V compounds for CMOS applications is being explored. The introduction of these new materials also opens the path towards the introduction of novel device structures which can be used to lower the supply voltage and reduce the power consumption. The results illustrate the possibilities that are created by the combination of new materials and devices to allow scaling of nanoelectronics beyond the Si roadmap.

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“…They associated this effect with incorporation of residual As in the Si interface layer. 7 A possible explanation of the above discrepancy was provided by our recent photoemission and transport results from Al/Si/GaAs͑001͒ diodes, 8,9 which showed that the As and Al fluxes required during Si deposition to produce an effect are much larger than those commonly employed for Si doping purposes, i.e., comparable with, or higher than the Si flux, and presumably higher than those employed by Koyanagi et al 7 Most empirical 6,10 and theoretical models 7,11,12 proposed to explain subsets of the above experimental results consider the electronic structure of the Si interfacial layer as identical to that of bulk Si, require the presence of an As-doped ͑Ga-doped͒ n ϩ (p ϩ ) degenerate Si layer of sufficient thickness at the interface, e.g., to justify tunneling, 6 compensation, 7,10 or metallic screening of the interface states, 12 and assume that the band alignment across the Si-GaAs heterojunction in the Al/Si/GaAs structure is independent of the Si layer thickness. Conversely, no substantial change of the Schottky barrier relative to the Al/n-GaAs͑001͒ case was reportedly observed in Al/Si/n-GaAs͑001͒ structures in which Si layers 10-40 Å thick had been grown under Ga flux.…”

Section: Introductionmentioning

confidence: 95%

Tunable Schottky barriers and the nature of Si interface layers in Al/GaAs(001) diodes

Sorba¹

1996

Journal of Vacuum Science &Amp; Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena

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Articles you may be interested inStudy on the interfaces of Cu/PA-N and PA-N/Si by secondary ion mass spectroscopy and scanning electron microscopy J.Effect of Al ion implantation on the adhesion of Al films to SiO2 substrates High-temperature stable Ir-Al/n-GaAs Schottky diodes: Effect of the barrier height controlling Silicon layers grown by molecular beam epitaxy in the interface region of Al/n-GaAs͑001͒ Schottky diodes have been shown to tune the Schottky barrier height in the 0.3-1.1 eV range, provided that high enough excess fluxes of As or Al are employed during Si deposition. We studied the incorporation of As and Al in the interface layer for Si growth temperatures of 300 and 400°C, and for interlayer thicknesses in the 10-150 Å range. Following deposition under an excess As flux we found an As atomic concentration c As ϭ0.4 -0.5 at 300°C and c As ϭ0.2 at 400°C. The excess Al flux yielded an Al atomic concentration c Al ϭ0.7-0.8 at 300°C, and c Al ϭ0.6 -0.7 at 400°C. Correspondingly, the lattice structure of the interlayers appears dramatically different from that of Si. We conclude that the 10-100 Å interface layers used by some authors to change the barrier height bear little resemblance to degenerate bulk Si, so that several of the mechanisms proposed to explain Schottky barrier tuning should be reevaluated.

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Unpinning the GaAs Fermi level with thin heavily doped silicon overlayers

Cited by 21 publications

References 9 publications

Gate quality Si3N4 prepared by low temperature remote plasma enhanced chemical vapor deposition for III–V semiconductor-based metal–insulator–semiconductor devices

Gate quality Si3N4 prepared by low temperature remote plasma enhanced chemical vapor deposition for III–V semiconductor-based metal–insulator–semiconductor devices

Shaping the future of nanoelectronics beyond the Si roadmap with new materials and devices

Tunable Schottky barriers and the nature of Si interface layers in Al/GaAs(001) diodes

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