Universal NBTI Compact Model for Circuit Aging Simulation under Any Stress Conditions

This paper proposes dynamic and long-term negative bias temperature instability (NBTI) model for predicting circuit degradation. The real-time dynamic simulation is carried out by implementing the NBTI model into the compact MOSFET model HiSIM. Since this simulation approach is time consuming, a long-term model is developed, which enables to predict the device degradation after 10 years' usage. The aged device characteristics are able to be directly calculated from determined operation time, frequency and duty cycle.

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“…The accuracy of the developed model has been verified in our previous work [8] with huge amount of different static measurement data.…”

Section: Dynamic Nbti Modelmentioning

confidence: 63%

“…We have developed a universal NBTI model with descriptions of the interface-state generation and the hole-trapping mechanisms [8]. As illustrated in Fig.…”

Section: Introductionmentioning

confidence: 99%

Modeling of aging effect for advanced MOSFETs

Mattausch

Matsuzawa

et al. 2014

2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

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“…The simulation is performed with the default set of BSIM6 parameters which corresponds to a 65 nm CMOS SOl process. For HCI a Bravaix-like model [2] and for BTl the model from [6] is used. As behavioral language Verilog-A is applied.…”

Section: Resultsmentioning

confidence: 99%

Charge-based stochastic aging analysis of CMOS circuits

Hillebrand

Hellwege

Heidmann

et al. 2015

2015 IEEE International Integrated Reliability Workshop (IIRW)

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Scaled down CMOS transistors are prone to degra dation and process variation. This necessitates a transistor model that provides an insight into the internal dependencies between these two crucial effects. Models for modern transistors and their degradation behavior are hardly attachable. This paper proposes a modified BSIM6 model which includes degradation due to BTl and HCI and in addition process variations. The application of this method is demonstrated on the basis of a single MOSFET and an inverter stage. The results can be used in the grn/1d work flow or for yield estimation on circuit level.

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“…For this short term reversible trapping behavior that does not involve metastable state creation [22], the rate of trap filling can be given by Refs. [23,24].…”

Section: Determining the Charge Trapping Ratementioning

confidence: 99%