Unifying manycore and FPGA processing with the RUSH architecture

Abstract

Because of the constraints of space computing, the set of available processing technologies is limited. Conventionally, designers have had to choose from programmable radhard processors and fixed ASIC solutions. FPGAs provide significantly better power-performance efficiency than general purpose processors, but are more costly to program and are less flexible. For terrestrial applications, manycore processors have been adopted for a class of applications where both performance and flexible programmability are important metrics. Maestro, the first rad-hard manycore processor, has the potential to enable new capabilities for space computation. However, for many applications, certain timing-critical tasks still require the performance efficiency of an FPGA co-processor. Moreover, integrating such heterogeneous systems is challenging because the individual processing substrates have differing internal programming models. As a result, data sharing and dynamic workload scheduling across heterogeneous architectures are often suboptimal and hindered by poor scalability. The Rad-hard Unified Scalable Heterogeneous (RUSH) architecture is a heterogeneous processing platform with both a manycore chip and an FPGA. RUSH provides a unified programming model across both chips to allow for rapid development of scalable and efficient implementations. This paper overviews RUSH's technical approach and presents an example application: a WiMAX radio transceiver.

Performance of a Hardware Scheduler for Many-core Architecture

“…Multiple identical, programmable tiles having local caches are connected by multiple mesh NoCs. Extensions are proposed in [19] [20], and a use case is presented in [21]. It employs static compile time scheduling [9] that orchestrates parallelism within a basic block across tiles and also handles control flow across basic blocks.…”