Unified defect model and beyond

Abstract

The unified defect model has been successful in explaining a wide variety of phenomena as oxygen or a metal is added to the III–V surface. These phenomena cover a range from a small fraction of a monolayer of adatoms to practical III–V structures with very thick overlayers. The tenets of the unified defect model are outlined, and the experimental results leading to its formulation are briefly reviewed. InP levels 0.4 and 0.1 eV and GaAs levels 0.7 and 0.9 eV below the conduction-band minimum (CBM) are associated with either missing column III or V elements. In InP, it has been found possible by a number of workers to ’’switch’’ between the two defect levels by variations in surface processing, temperature, and/or selection of the deposited atom. The need to apply the proper concepts for surface and interface chemistry and metallurgy is recognized, and the danger of using solely bulk concepts is emphasized. The reason for this is examined for certain cases on an atomic level. The need for new fundamental attacks on interface interaction is shown. The importance of semiconductor–oxide chemical stability is also recognized and, drawing on a large body of work from several laboratories, it is suggested that there will be more difficulties with ’’native’’ oxides on GaAs than on InP. It is concluded that ’’scientific engineering’’ of interfaces to give optimum performance should be a goal and test of the fundamental work described here. Specific possibilities are discussed for Schottky barriers on III–V’s.

X-ray photoemission determination of the Schottky barrier height of metal contacts to n–GaN and p–GaN

“…Spicer et al proposed the unified defect model, in which the deposition of metal atoms creates defects on the semiconductor surface that give rise to donorlike and acceptorlike states. [47][48][49] This mechanism would lead to a separate pinning position for nand p-GaN, as observed for Au, Ti, and Pt overlayers. This is consistent with our choice of chemical treatments for the samples prior to metallization.…”

Temperature and frequency dependent electrical characterization of HfO2/InxGa1−xAs interfaces using capacitance-voltage and conductance methods

“…Atomic identification of the defects is beyond the capabilities of the electrical characterization techniques used in the present study. 16 In the case of the In 0.53 Ga 0.47 As stack, the dispersion observed in the CV as a function of both temperature and frequency, for V gate in the range of Ϫ1 V to Ϫ4 V, is characteristic of interface defects and is unlikely to be representative of true inversion at the HfO 2 / In 0.53 Ga 0.47 As interface. 17 Similar frequency dependent CV profiles to those in the inset to Fig.…”

Frequency dispersion in III-V metal-oxide-semiconductor capacitors

“…The interface trap state distribution in the band gap depends largely on the specific III-V semiconductor. [3][4][5][6] For example, the D it of dielectric/n-In 0.53 Ga 0.47 As interfaces is sufficiently low to achieve band bending (semiconductor Fermi level movement) in the upper half of the semiconductor band gap under an applied voltage, 7,8 resulting in significant device demonstrations. 9,10 One of the most important unresolved issues, however, remains the lack of understanding of the large frequency dispersion that is observed in accumulation, for example, for dielectrics on n-In 0.53 Ga 0.47 As.…”