Unequal-Error-Protection Error Correction Codes for the Embedded Memories in Digital Signal Processors

Tang, Hoyoung

doi:10.1109/tvlsi.2015.2497368

Cited by 2 publications

(5 citation statements)

References 10 publications

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“…11(a). For B = 8, a (15,11) Hamming code cannot be incorporated into an 8-bit word. Hence, we store four parity bits of a Hamming (15,11) codeword in the last LSBs of four different 8-bit words as proposed in [18].…”

Section: Numerical Resultsmentioning

confidence: 99%

“…For B = 8, a (15,11) Hamming code cannot be incorporated into an 8-bit word. Hence, we store four parity bits of a Hamming (15,11) codeword in the last LSBs of four different 8-bit words as proposed in [18]. Note that selective ECC (15,11) for B = 8 converges to LSB dropping (L = 1) for high E(∆) since both schemes discard only the last LSBs.…”

Section: Numerical Resultsmentioning

confidence: 99%

“…3) Unequal error protection (UEP) by error control codes (ECCs) [14], [15], 4) LSB dropping (dropping the LSBs at the cost of reduced arithmetic precision) [16]- [18].…”

mentioning

confidence: 99%

“…Practical implementations only allow a few supply voltage levels [12], [13]. Fine-grained UEP [14], [15] requires complicated hardware implementations and dynamic change of protection is limited. LSB dropping [16]- [18] enables dynamic fidelity control by changing the number of dropped LSBs.…”

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confidence: 99%

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Generalized Water-filling for Source-aware Energy-efficient SRAMs

Kim

Kang

Varshney

et al. 2018

IEEE Trans. Commun.

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Conventional low-power static random access memories (SRAMs) reduce read energy by decreasing the bit-line voltage swings uniformly across the bit-line columns. This is because the read energy is proportional to the bit-line swings. On the other hand, bit-line swings are limited by the need to avoid decision errors especially in the most significant bits. We propose a principled approach to determine optimal non-uniform bit-line swings by formulating convex optimization problems. For a given constraint on mean squared error of retrieved words, we consider criteria to minimize energy (for low-power SRAMs), maximize speed (for high-speed SRAMs), and minimize energy-delay product.These optimization problems can be interpreted as classical water-filling, ground-flattening and waterfilling, and sand-pouring and water-filling, respectively. By leveraging these interpretations, we also propose greedy algorithms to obtain optimized discrete swings. Numerical results show that energyoptimal swing assignment reduces energy consumption by half at a peak signal-to-noise ratio of 30dB for an 8-bit accessed word. The energy savings increase to four times for a 16-bit accessed word. I. INTRODUCTIONVon Neumann computing architectures separate memory units from computing units so there is frequent data access that consumes enormous energy. Since static random access memories (SRAMs) access requires more energy than arithmetic operations [1], SRAM access energy accounts for the significant part of the total energy consumption in many information processing This work was supported in part by Systems on Nanoscale Information fabriCs (SONIC), one of the six SRC STARnet Centers, sponsored by MARCO and DARPA. arXiv:1710.07153v3 [cs.IT] 29 Nov 2017 formulate convex optimization problems whose objectives are as follows: C1. Minimize energy (low-power SRAMs), C2. Maximize speed (high-speed SRAMs), C3. Minimize energy-delay product (EDP).Solutions to these convex problems yield optimal performance that is theoretically attainable.By casting read access for SRAMs as communication over parallel channels, we investigate the fundamental trade-offs between physical resources (energy, delay, and EDP) and a fidelity (MSE) constraint.In addition, we provide generalized water-filling interpretations for our optimal solutions. This follows since accessing a B-bit word is equivalent to communicating information through B parallel channels. In classical water-filling, the ground represents the noise levels of parallel channels [20], [21]. On the other hand, the importance of each bit position determines the ground level in our optimization problems. Each optimization problem has its own interpretation depending on its objective function: water-filling (C1), ground-flattening and water-filling (C2), and sand-pouring and water-filling (C3), respectively. We also observe interesting connections between our problems and variants on water-filling such as constant-power water-filling [22],[23] and mercury/water-filling [24]. Also, we show that the proposed ...

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Section: Numerical Resultsmentioning

confidence: 99%

Section: Numerical Resultsmentioning

confidence: 99%

“…3) Unequal error protection (UEP) by error control codes (ECCs) [14], [15], 4) LSB dropping (dropping the LSBs at the cost of reduced arithmetic precision) [16]- [18].…”

mentioning

confidence: 99%

mentioning

confidence: 99%

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Generalized Water-filling for Source-aware Energy-efficient SRAMs

Kim

Kang

Varshney

et al. 2018

IEEE Trans. Commun.

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“…In addition to the main thread, FERNANDO creates two redundant threads (Rthread1 and Rthread2) on two spare cores to redundantly execute the original program. Assuming that memory and cache are already effectively protected by widely used Error Correction Codes (ECC) [15], [31], [32], FERNANDO focus on errors inside the microprocessor, such as pipeline register, function units, and register file. As with all existing software RMT error resilience techniques [15][16][17][18][19][20], we focus on protecting the application instructions and function calls.…”

Section: Our Solution: Fernandomentioning

confidence: 99%

FERNANDO: A Software Transient Fault Tolerance Approach for Embedded Systems Based on Redundant Multi-Threading

Guo

2021

IEEE Access

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As semiconductor technology scales, modern microprocessors are more vulnerable to transient faults. Software-level fault tolerance schemes are promising because they can improve reliability effectively without extra hardware. Redundant Multi-threading (RMT) uses off-the-shelf cores as redundancy to achieve error resilience. Latest software RMT fault-tolerance models do not effectively cope with transient faults occurring on multiple components during the application execution, resulting in a large number of silent data corruptions (SDC). To address this challenge, we propose FERNANDO, a software-level RMT runtime fault tolerance scheme which provides enhanced error detection and comprehensive error recovery by Triple-Modular Redundancy (TMR). On an ARM Cortex-A57 like simulated microprocessor, we performed probability model transient fault injection experiments in different components of all cores. The results demonstrate that, compared to the state-of-the-art technique, FERNANDO can reduce the SDC rate by about 86.67 percent and optimize the execution time overhead by about 19.64 percent.

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Unequal-Error-Protection Error Correction Codes for the Embedded Memories in Digital Signal Processors

Cited by 2 publications

References 10 publications

Generalized Water-filling for Source-aware Energy-efficient SRAMs

Generalized Water-filling for Source-aware Energy-efficient SRAMs

FERNANDO: A Software Transient Fault Tolerance Approach for Embedded Systems Based on Redundant Multi-Threading

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