Understanding the Effect of Process Variations on the Delay of Static and Domino Logic

An SEU resilient, SET filterable and cost effective latch in presence of PVT variations

“…The first and perhaps most important reason is that, the proposed latch does not have active positive feedback loops while most of the other latches listed in Table 1 suffer this problem to some extent when work in transparent mode. It is well known from feedback theory that positive feedback loop increases the sensitivity to PVT variations [27,28]. Furthermore, the ISST embedded in the proposed latch can increase the margin of threshold voltage due to its hysteresis property, which reduces the effects of PVT variations.…”

CMOS Form of Wallace Range Exploitation Domino Logic Full Adder

“…Massimo Alioto, Gaetato Palumbo, Melita Pennisi [6] In this paper, the effect of process variations on delay is analyzed in depth for both static and dynamicCMOSlogic styles. Analysis allows for gaining an insight into the delay dependence on fan-in, fan-out, and sizing in sub-100-nm technologies.…”

An analytical approach to efficient circuit variability analysis in scaled CMOS design

“…An analytical model for delay variation is derived in [6] where the nominal delay equations are based the α-power model. Here gates with stacked transistors are simplified to equivalent inverters, so variation because of different inputs cannot be characterized.…”

“…While there are many analytical models [25,26,31] to predict nominal delays, these models do not analyze effect of process variations, which is critical for future technology nodes. The existing work on variability analysis are either not accurate [6] or do not provide analytical models for fast estimation [20]. In contrast, this thesis proposes a model that is very accurate and provides a fast way to analyze variability in complex CMOS circuits.…”