Understanding Delta‐Sigma Data Converters

Pavan, Shanti; Schreier, Richard; Temes, Gábor C.

doi:10.1002/9781119258308

Cited by 828 publications

(229 citation statements)

References 14 publications

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“…But if adopting CIC filter directly, the coefficients for V f and V s in h(n) are not symmetric and the CIC filter needs to be truncated by rectangle window to satisfy the symmetric requirement. Generally, to achieve better filtering performance, the order of CIC filter should be at least one order higher than that of modulator [18]. In addition, the length of CIC filter should be even and symmetric, so the fifth-order CIC filter is chosen.…”

Section: ) Differential Cascade Of Integrators (Dcoi) Filtermentioning

confidence: 99%

A Fully Integrated 0.055% INL X-ray CCD Readout ASIC with Incremental <inline-formula> <tex-math notation="LaTeX">$\Delta \Sigma {\text{ADC}}$</tex-math> </inline-formula>

Wang

Cao

et al. 2016

IEEE Trans. Nucl. Sci.

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A fully integrated 100 kHz X-ray charge coupled device (CCD) readout application specific integrated circuit (ASIC) employing delta sigma (ΔΣ) digitization is presented. To achieve high linearity with small chip size and low power consumption, the correlated double sampling (CDS) is realized by the ΣΔADC instead of the analog front end (AFE) as in conventional CCD readout circuits. Besides, the proposed decimation filter features simple structure and eases the integration. The chip is fabricated in 0.35 µm CMOS technology and the measured integral nonlinearity (INL) throughout the input dynamic range of ASIC is 0.055% with 35.1 ± 0.3 µV input referred noise. A CCD detection system is built and tested with the sensitivity of CCD being 4 µV/e − . The integration test results show that the readout noise is 11.8 e − at 100 kHz readout pixel rate and the achieved energy spectrum resolution is 168 eV ± 4.7 eV (Full Width at Half Maximum: FWHM) at 5.9 keV.Index Terms-ASIC, CCD readout, incremental ΣΔADC, low noise.

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Section: ) Differential Cascade Of Integrators (Dcoi) Filtermentioning

confidence: 99%

A Fully Integrated 0.055% INL X-ray CCD Readout ASIC with Incremental <inline-formula> <tex-math notation="LaTeX">$\Delta \Sigma {\text{ADC}}$</tex-math> </inline-formula>

Wang

Cao

et al. 2016

IEEE Trans. Nucl. Sci.

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“…In this case the quantization noise is usually treated as zero mean white noise [3]. This substitution yields the following linear equation…”

Section: Multi-step Look-ahead Optimization Algorithm a σ-δ Modumentioning

confidence: 99%

“…Due to the fact that Σ-Δ modulation is a non-linear process, its analysis is particularly difficult and is usually based on linear or quasi-linear models. Many empirical stability criteria and optimization techniques can be found in [3], while a stability analysis of high-order Σ-Δ modulators is presented in [4]. Stability problems relate to the input amplitude, the loop filter zeros and poles and the number of quantization levels.…”

Section: Introductionmentioning

confidence: 99%

“…Stability problems relate to the input amplitude, the loop filter zeros and poles and the number of quantization levels. An increase in the number of quantization levels improves stability [3], but a multi-bit output necessitates the use of a DAC in the case of a direct all-digital frequency synthesizer or a more complicated frequency divider in a fractional-N PLL.…”

Section: Introductionmentioning

confidence: 99%

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Single-bit-output all-digital frequency synthesis using multi-step look-ahead bandpass Σ-Δ modulator-like quantization processing

Basetas

Sotiriadis

2015

2015 Joint Conference of the IEEE International Frequency Control Symposium &Amp; The European Frequency and Time Forum

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A configurable single-bit-output Σ-Δ modulator variant is presented, which improves upon stability and dynamic range. The derivation of the proposed modulation scheme from the Σ-Δ error-feedback structure and its mathematical description are analyzed, while its application in fractional-N frequency dividers and all-digital frequency synthesizers is investigated. It is shown that stable high-order noise shaping is possible even when using noise transfer functions that are unstable in a conventional Σ-Δ modulator loop. Furthermore, multipliers can be avoided if the noise transfer function coefficients are chosen appropriately, leading to a low complexity hardware implementation. In special cases the architecture is equivalent to another Σ-Δ modulator with a different, stable, NTF than the initial one. The effectiveness of the proposed modulation scheme is demonstrated by specific examples for each application.978-1-4799-8866-2/15/$31.00 ©2015 IEEE

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“…Figure 10: Band-Pass Σ/Δ modulator Assuming for now (only) that the quantizer is equivalent to an addition with a quantization noise sequence ( ) Fig. 11 from [6]. A challenge with this choice is that ( ) F z must be changed when the desirable frequency Ω changes (and the band of interest around it).…”

Section: IImentioning

confidence: 99%

All digital frequency synthesis based on new sigma-delta modulation architectures

Sotiriadis

2015

2015 Joint Conference of the IEEE International Frequency Control Symposium &Amp; The European Frequency and Time Forum

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Understanding Delta‐Sigma Data Converters

Cited by 828 publications

References 14 publications

A Fully Integrated 0.055% INL X-ray CCD Readout ASIC with Incremental <inline-formula> <tex-math notation="LaTeX">$\Delta \Sigma {\text{ADC}}$</tex-math> </inline-formula>

A Fully Integrated 0.055% INL X-ray CCD Readout ASIC with Incremental <inline-formula> <tex-math notation="LaTeX">$\Delta \Sigma {\text{ADC}}$</tex-math> </inline-formula>

Single-bit-output all-digital frequency synthesis using multi-step look-ahead bandpass Σ-Δ modulator-like quantization processing

All digital frequency synthesis based on new sigma-delta modulation architectures

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Understanding Delta‐Sigma Data Converters

Cited by 828 publications

References 14 publications

A Fully Integrated 0.055% INL X-ray CCD Readout ASIC with Incremental <inline-formula> <tex-math notation="LaTeX">$\Delta \Sigma {\text{ADC}}$</tex-math> </inline-formula>

A Fully Integrated 0.055% INL X-ray CCD Readout ASIC with Incremental <inline-formula> <tex-math notation="LaTeX">$\Delta \Sigma {\text{ADC}}$</tex-math> </inline-formula>

Single-bit-output all-digital frequency synthesis using multi-step look-ahead bandpass &#x03A3;-&#x0394; modulator-like quantization processing

All digital frequency synthesis based on new sigma-delta modulation architectures

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Single-bit-output all-digital frequency synthesis using multi-step look-ahead bandpass Σ-Δ modulator-like quantization processing