2016
DOI: 10.1145/2870636
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Understanding and Mitigating Covert Channels Through Branch Predictors

Abstract: Covert channels through shared processor resources provide secret communication between two malicious processes: the trojan and the spy. In this article, we classify, analyze, and compare covert channels through dynamic branch prediction units in modern processors. Through experiments on a real hardware platform, we compare contention-based channel and the channel that is based on exploiting the branch predictor's residual state. We analyze these channels in SMT and single-threaded environments under both clea… Show more

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Cited by 65 publications
(25 citation statements)
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“…In addition to targeting cryptographic algorithms, side channels on the BPU can be used to perform other types of side-channel attacks, such as deriving kernel and userlevel ASLR offset [33], or covert channels [34], [35]. Recently, a side-channel attack on directional branch predictors was proposed [14].…”
Section: Microarchitectural Side-channel Attacksmentioning
confidence: 99%
“…In addition to targeting cryptographic algorithms, side channels on the BPU can be used to perform other types of side-channel attacks, such as deriving kernel and userlevel ASLR offset [33], or covert channels [34], [35]. Recently, a side-channel attack on directional branch predictors was proposed [14].…”
Section: Microarchitectural Side-channel Attacksmentioning
confidence: 99%
“…Our BHB channel is the same as the residual state-based covert channel [Evtyushkin et al 2016], where the sender sends information by either taking or skiping a conditional jump instruction. The receiver measures the latency on a similar conditional jump instruction, sensing any speculative execution caused by the sender's history.…”
Section: Platform Cache Raw Full Flush Protectedmentioning
confidence: 99%
“…Microarchitectural side-channel attacks. CPU sidechannel attacks [12,18,27,39,43,68,74] are well-studied, leading to defenses based on static or dynamic partitioning of caches [11,21,22,53,69], OS-and compiler-supported cache line locking [33,69], randomization of replacement [70] and fill [38] policies, timing noise injection [41], or managing traffic at the memory controller [59,67,76]. Covert Channels using shared GPU hardware [45] are a nascent area, including AES Key extraction using shared GPU hardware [24,25].…”
Section: Background and Related Workmentioning
confidence: 99%