Underfill process for two parallel plates and flip chip packaging

Khor, C. Y.; Abdullah, M. Z.; Ani, F. Che

doi:10.1016/j.icheatmasstransfer.2012.07.006

Cited by 15 publications

(7 citation statements)

References 21 publications

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“…There has been considerable amount of underfill researche studies on the process optimization and improvement, mainly to address the manufacturing productivity issue of long filling time (Young, 2011; Khor and Abdullah, 2012). Among the design parameters being investigated in the past optimization studies are gap height (Khor et al , 2012), bump pitch (Young and Yang, 2002; Lee et al , 2010; Kim et al , 2011), contact angle (Young and Yang, 2006) and bump arrangement (Khor et al , 2010). Consistent to the current trend of package’s miniaturization, bump pitch was the most sought-after parameter in the past optimization studies.…”

Section: Introductionmentioning

confidence: 99%

Spatial analysis of underfill flow in flip-chip encapsulation

Zawawi

Abas

2020

SSMT

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Purpose The purpose of the study is to investigate the spatial aspects of underfill flow during the flip-chip encapsulation process, for instance, meniscus evolution and contact line jump (CLJ). Furthermore, a spatial-based void formation mechanism during the underfill flow was formulated. Design/methodology/approach The meniscus evolution of underfill fluid subtended between the bump array and the CLJ phenomenon were visualized numerically using the micro-mesh unit cell approach. Additionally, the meniscus evolution and CLJ phenomenon were modelled analytically based on the formulation of capillary physics. Meanwhile, the mechanism of void formation was explained numerically and analytically. Findings Both the proposed analytical and current numerical findings achieved great consensus and were well-validated experimentally. The variation effects of bump pitch on the spatial aspects were analyzed and found that the meniscus arc radius and filling distance increase with the pitch, while the subtended angle of meniscus arc is invariant with the pitch size. For larger pitch, the jump occurs further away from the bump entrance and takes longer time to attain the equilibrium meniscus. This inferred that the concavity of meniscus arc was influenced by the bump pitch. On the voiding mechanism, air void was formed from the air entrapment because of the fluid-bump interaction. Smaller voids tend to merge into a bigger void through necking and, subsequently, propagate along the underfill flow. Practical implications The microscopic spatial analysis of underfill flow would explain fundamentally how the bump design will affect the macroscopic filling time. This not only provides alternative visualization tool to analyze flow pattern in the industry but also enables the development of accurate analytical filling time model. Moreover, the void formation mechanism gave substantial insights to understand the root causes of void defects and allow possible solutions to be formulated to tackle this issue. Additionally, the microfluidics sector could also benefit from these spatial analysis insights. Originality/value Spatial analysis on underfill flow is scarcely conducted, as the past research studies mainly emphasized on the temporal aspects. Additionally, this work presented a new mechanism on the void formation based on the fluid-bump interaction, in which the formation and propagation of micro-voids were numerically visualized for the first time. The findings from current work provided fundamental information on the flow interaction between underfill fluid and solder bump to the package designers for optimization work and process enhancement.

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Section: Introductionmentioning

confidence: 99%

Spatial analysis of underfill flow in flip-chip encapsulation

Zawawi

Abas

2020

SSMT

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“…In the design optimization of flip-chips, the bump pitch was found to be the most studied parameter (Young and Yang, 2002;Lee et al, 2010;Yao et al, 2014;Ng et al, 2019a), followed by gap height (Khor et al, 2012a) and contact angle (Young and Yang, 2006). This was aligned with the miniaturization need and consistent with the current trend of developing smaller, yet better performance devices (Ng et al, 2016).…”

Section: Introductionmentioning

confidence: 73%

Filling efficiency of flip-chip underfill encapsulation process

Abas

Abdullah

2019

SSMT

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Purpose This paper aims to introduce a new indicative parameter of filling efficiency to quantify the performance and productivity of the flip-chip underfill encapsulation process. Additionally, the variation effect of the bump pitch of flip-chip on the filling efficiency was demonstrated to provide insight for flip-chip design optimization. Design/methodology/approach The filling efficiency was formulated analytically based on the conceptual spatial and temporal perspectives. Subsequently, the effect of bump pitch on filling efficiency was studied based on the past actual-scaled and current scaled-up underfill experiments. The latter scaled-up experiment was validated with both the finite volume method-based numerical simulation and analytical filling time model. Moreover, the scaling validity of scaled-up experiment was justified based on the similarity analysis of dimensionless number. Findings Through the scaling analysis, the current scaled-up experimental system is justified to be valid since the adopted scaling factor 40 is less than the theoretical scaling limit of 270. Furthermore, the current experiment was qualitatively well validated with the numerical simulation and analytical filling time model. It is found that the filling efficiency increases with the bump pitch, such that doubling the bump pitch would triple the efficiency. Practical implications The new performance indicative index of filling efficiency enables the package designers to justify the variation effect of underfill parameter on the overall underfill process. Moreover, the upper limit of scaling factor for scaled-up package was derived to serve as the guideline for future scaled-up underfill experiments. Originality/value The performance of underfill process as highlighted in this paper was never being quantified before in the past literatures. Similarly, the scaling limit that is associated to the scaled-up underfill experiment was never being reported elsewhere too.

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“…The uid motion is described by continuity and momentum equations [13]. The uid temperature is expressed by an energy equation.…”

Section: Fluid Ow Modelingmentioning

confidence: 99%

“…This fraction was used to evaluate the lling level of the molten solder. It was also used to evaluate liquid phase in various CFD applications [13][14][15][16]. Wetting the PCB surface is important during wave soldering.…”

Section: Fluid Ow Modelingmentioning

confidence: 99%

Influence of printed circuit board thickness in wave soldering

et al. 2017

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Abstract. This paper presents a thermal Fluid-Structure Interaction (FSI) study of Printed Circuito Bards (PCBs) during wave soldering. The in uences of PCB thickness on displacement, stress, and temperature distribution are the foci of this study. Five PCB thicknesses (i.e., 0.6, 1.0, 1.6, 2.4, and 3.1 mm) are considered. The paper focuses on a simple PCB with a single hole and is constructed in a three-dimensional model. The thermal FSI of the PCB is solved by uid (FLUENT) and structure (ABAQUS) solvers that are connected using the mesh-based parallel code coupling interface method. Molten solder advancement is tracked using volume-of-uid technique in the thermal uid analysis. ABAQUS solves PCB displacement, von Mises stress, and temperature distributions when high solder temperature is encountered during wave soldering. The correlations of PCB thickness with displacement, von Mises stress, temperature distribution, and molten solder lling time are studied. Results reveal that an increase in PCB thickness yields a linear correlation with solder lling time. Temperature distribution, von Mises stress, and displacement of PCB exhibit polynomial behavior to PCB thickness. A laboratory-scale two-way wave-soldering machine is also used to measure PCB temperature during wave soldering. The predicted temperature of PCB is substantiated by the experimental results.

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Underfill process for two parallel plates and flip chip packaging

Cited by 15 publications

References 21 publications

Spatial analysis of underfill flow in flip-chip encapsulation

Spatial analysis of underfill flow in flip-chip encapsulation

Filling efficiency of flip-chip underfill encapsulation process

Influence of printed circuit board thickness in wave soldering

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