UML-based analysis of embedded systems using a mapping to VHDL

McUmber, W.E.; Cheng, Betty H. C.

doi:10.1109/hase.1999.809475

Cited by 47 publications

(21 citation statements)

References 10 publications

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“…In addition, e is a flexible language with growing tool support [8] and is used by our collaborators in the automotive semiconductor industry, providing a source of early industry feedback on our work. By initially focusing on a single verification language it is possible to support current development techniques in terms of design and verification language, reducing the burden of learning a new set of tools and languages [28].…”

Section: Hardware Verification Languagesmentioning

confidence: 99%

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An aspect-oriented, model-driven approach to functional hardware verification

Linehan

Clarke

2012

Journal of Systems Architecture

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The cost of correcting errors in the design of an embedded system's hardware components can be higher than for its software components, making it important to test as early as possible. Testing hardware components before they are implemented involves verifying the design through either formal or more commonly, simulation-based functional verification. Performing functional verification of a hardware design requires software-based simulators and verification testbenches. However, the increasing complexity of embedded systems is contributing to testbenches that are progressively more difficult to understand, maintain, extend and reuse across projects. This paper presents an aspect-oriented domainspecific modelling language for the e hardware verification language that can be used as part of a model-based software engineering process. The modelling language is designed to produce well modularised models from which e code can be generated, thereby improving engineers ability to develop testbenches that can be more easily maintained, adapted and reused. We demonstrate the suitability of the modelling language through its application to a representative testbench from the automotive semiconductor industry.

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Section: Hardware Verification Languagesmentioning

confidence: 99%

“…McUmber at al. also make use of UML class and state diagrams to specify both structure and behaviour [28]. In their case VHDL specifications are generated by applying a set of rules for mapping from UML to VHDL.…”

Section: Related Workmentioning

confidence: 99%

An aspect-oriented, model-driven approach to functional hardware verification

Linehan

Clarke

2012

Journal of Systems Architecture

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“…Rational Rose 2 and Artisan Studio 3 ) that can generate software code from UML models. However, considering embedded systems' hardware part, only few works address the use of UML to produce Hardware Description Language (HDL) descriptions, as in [9], [10]. In this sense, the transformation of UML models into HDL code, e.g.…”

Section: Introductionmentioning

confidence: 99%

Generating VHDL Source Code from UML Models of Embedded Systems

Moreira¹,

Wehrmeister

Pereira

et al. 2010

Distributed, Parallel and Biologically Inspired Systems

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Abstract. Embedded systems' complexity and amount of distinct functionalities have increased over the last years. To cope with such issues, the projects' abstraction level is being continuously raised, and, in addition, new design techniques have also been used to shorten design time. In this context, ModelDriven Engineering approaches that use UML models are interesting options to design embedded systems, aiming at code generation of software and hardware components. Source code generation from UML is already supported by several commercial tools for software. However, there are only few tools addressing generation code using hardware description languages, such as VHDL. This work proposes an approach to generate automatically VHDL source code from UML specifications. This approach is supported by the GenERTiCA tool, which has been extended to support VHDL code generation. To validate this work, a use case focused in maintenance systems attended by embedded systems is presented.

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“…McUmber at al. also make use of UML class and state diagrams to specify both structure and behavior [McUmber and Cheng 1999]. In their case, VHDL specifications are generated by applying a set of rules for mapping from UML to VHDL.…”

Section: Related Workmentioning

confidence: 99%

Model-driven automation for simulation-based functional verification

Linehan

O'Toole

Clarke

2012

ACM Trans. Des. Autom. Electron. Syst.

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Developing testbenches for dynamic functional verification of hardware designs is a software intensive process that lies on the critical path of electronic system design. The increasing capabilities of electronic components is contributing to the construction of complex verification environments that are increasingly difficult to understand, maintain, extend and reuse across projects. Modeldriven software engineering addresses issues of complexity, productivity and code quality through the use of high-level system models and subsequent automatic transformations. Reasoning about verification testbench decomposition becomes simpler at higher levels of abstraction. In particular, the aspect-oriented paradigm, when applied at the model level can minimize the overlap in functionality between modules, improving maintainability and reusability. This paper presents an aspect-oriented model-driven engineering process and toolset for the development of hardware verification testbenches. We illustrate how this process and toolset supports modularized design and automatic transformation to verification environment-specific models and source code through an industry case study.

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UML-based analysis of embedded systems using a mapping to VHDL

Cited by 47 publications

References 10 publications

An aspect-oriented, model-driven approach to functional hardware verification

An aspect-oriented, model-driven approach to functional hardware verification

Generating VHDL Source Code from UML Models of Embedded Systems

Model-driven automation for simulation-based functional verification

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