Ultrathin Oxide Passivation Layer by Rapid Thermal Oxidation for the Silicon Heterojunction Solar Cell Applications

Abstract

It is difficult to deposit extremely thin a-Si:H layer in heterojunction with intrinsic thin layer (HIT) solar cell due to thermal damage and tough process control. This study aims to understand oxide passivation mechanism of silicon surface using rapid thermal oxidation (RTO) process by examining surface effective lifetime and surface recombination velocity. The presence of thin insulating a-Si:H layer is the key to get highVocby lowering the leakage current (I0) which improves the efficiency of HIT solar cell. The ultrathin thermal passivation silicon oxide (SiO2) layer was deposited by RTO system in the temperature range 500–950°C for 2 to 6 minutes. The thickness of the silicon oxide layer was affected by RTO annealing temperature and treatment time. The best value of surface recombination velocity was recorded for the sample treated at a temperature of 850°C for 6 minutes at O2flow rate of 3 Lpm. A surface recombination velocity below 25 cm/s was obtained for the silicon oxide layer of 4 nm thickness. This ultrathin SiO2layer was employed for the fabrication of HIT solar cell structure instead of a-Si:H, (i) layer and the passivation and tunneling effects of the silicon oxide layer were exploited. The photocurrent was decreased with the increase of illumination intensity and SiO2thickness.

Analysis of hydrogen distribution and migration in fired passivating contacts (FPC)

“…Note that the latter sample has to be considered as a reference, as such a stack with a homogenous 25 nm thick SiO2 layer could not be applied as contact. Unfortunately, growing a homogeneous, 1.3 nm thin thermal oxide at 900 °C is very challenging (and reducing the oxidation temperature affects the oxide quality [32]). Thus, a thickness of 25 nm was chosen, in order to enable comparison with the other experiments, where such thick thermal oxides were wanted.…”

On-Demand Fabrication of Si/SiO2 Nanowire Arrays by Nanosphere Lithography and Subsequent Thermal Oxidation

“…After Si NW arrays were fabricated, the following thermal oxidization technique was used to form SiO2 oxide layer on the surface of NWs. Compared with other SiO2 growth methods (i.e., plasma-enhanced chemical vapor deposition), the Si/SiO2 NWs prepared by thermal oxidation process have less surface defect density [ 14 , 22 ] and no undesirable Si–OH and Si–H bonds [ 23 , 24 ].…”

In Situ Process to Form Passivated Tunneling Oxides for Front-Surface Field in Rear-Emitter Silicon Heterojunction Solar Cells

“…One of the disadvantages of the oxide layers is the high barrier between the front surface field and the n-type c-Si heterointerface, as shown in Figure a. This high barrier can contribute to a high series resistance (RES s ), owing to the low probability of electrons tunneling through the oxide layer, leading to a low FF and unsatisfactory performance. , To evaluate the probability of electrons tunneling through our PTL, the TLM was employed under different CO 2 plasma treatment conditions. The specific contact resistance (ρ c ) derived from the TLM measurements as a function of the CO 2 plasma treatment is presented in Figure b.…”

“…This drawback can be addressed by employing wider bandgap materials, such as μc-Si:H and silicon tunneling oxide stacks, − as alternatives to the conventional a-Si:H stacks. , To form the wider bandgap-passivated silicon tunnel oxide, various methods have been investigated, such as wet and thermal oxidation and plasma-enhanced chemical vapor deposition (PECVD). Among these, the wet and thermal oxidation method exhibits disadvantages with respect to thickness control and the large valence-band offset at the heterointerface owing to the exceedingly large optical bandgap (∼9 eV), , in addition to a high processing temperature, which can cause wafer bending and entail high processing expenses. The devices based on the passivated silicon oxide deposited via PECVD suffer from a high series resistance, resulting in a low FF .…”