Ultrathin gate oxide CMOS on [111] surface-oriented Si substrate

Performance of polysilicon gate HfO2 MOSFETs on [100] and [111] silicon substrates

“…On the other hand, PMOS mobility on (111) substrates was higher than that of (100) substrates at higher effective fields. The high-field mobility dependence on the surface orientations was different between N and PMOSFETs, but it was consistent with that observed on SiO devices [5]. The PMOS mobility degradation of the (111) device at lower fields is attributed to enhanced Coulomb scattering due to the larger compared to the (100) device (Fig.…”

“…One of the possible experiments to investigate the mechanism of the inadequate mobility is comparing MOSFETs on different surface orientations. It is well known for the SiO devices that NMOSFET channel mobility on (111) substrates is lower than that of (100) substrates [4], while it is opposite for PMOSFETs [5]. This trend has remained unchanged as SiO thickness is scaled to 15 Å [5].…”

“…It is well known for the SiO devices that NMOSFET channel mobility on (111) substrates is lower than that of (100) substrates [4], while it is opposite for PMOSFETs [5]. This trend has remained unchanged as SiO thickness is scaled to 15 Å [5]. Since most of the reported HfO devices were fabricated on (100) substrates, the comparison between different surface orientations might provide some insight regarding whether the mobility degradation is solely dominated by the quality of high-gate dielectrics.…”

Influence of surface orientation on electrical characteristics in MOSFETs with slightly tilted off-axis channel

“…However, there have been few reports on the properties of MOSFETs with off-axis channel to Si plane other than (100) oriented Si plane [4][5]. This paper reviews electrical characteristics in pand n-MOSFETs with slightly tilted off-axis (110) channel [6].…”

Impact of gate-leakage currents on CMOS circuit performance

“…By keeping with ''conventional'' structures, reliable design flows and tools can be more straightforwardly exploited, allowing for effective design of large VLSI chips. A number of excellent studies can be found in the literature [3][4][5], which investigate the behaviour of such thin gate-oxide devices; however, impacts of gateleakage currents at the circuit-and system level is less documented: in this work, we try to analyse such impact, with respect to further scaling of SiO 2 planar CMOS technology, beyond current state-of-the art. To this purpose, a mixed-mode analysis flow has been devised and implemented, which allows for evaluating direct correlation of major circuit-performance indices to the actual oxide thickness (t ox ) and to other fabrication parameters.…”