Ultrathin Al‐Assisted Al₂O₃ Passivation Layer for High‐Stability Tungsten Diselenide Transistors and Their Ambipolar Inverter (Adv. Electron. Mater. 4/2022)

Abstract

Transition Metal Dichalcogenides Seongin Hong, Sunkook Kim, and colleagues present the first report which not only proposes a novel approach to improve the stability of two‐dimensional transition metal dichalcogenides based field‐effect transistors but also implements a complementary metal oxide semiconductor inverter circuit using it. In article number 2101012, the authors develop high‐stability tungsten diselenide field‐effect transistors with an ultrathin Al‐assisted alumina passivation.

Se-Vacancy Healing with Substitutional Oxygen in WSe2 for High-Mobility p-Type Field-Effect Transistors

“…Moreover, the exploration of p-type TMDs is essential for practical CMOS architecture development because research on tungsten diselenide (WSe 2 ) has recently gained attention. WSe 2 is considered to be a promising material for CMOS logic circuit applications because its n-p polarity can be easily adjusted . However, it is still difficult to fundamentally solve the mobility degradation of WSe 2 transistors.…”

“…WSe 2 is considered to be a promising material for CMOS logic circuit applications because its n-p polarity can be easily adjusted. 7 However, it is still difficult to fundamentally solve the mobility degradation of WSe 2 transistors. Unfortunately, carrier mobility is exacerbated by many scattering mechanisms, such as structural defects, including subtrap states, phonons, and Coulomb impur- ities.…”

Ultimate Limit in Optoelectronic Performances of Monolayer WSe2 Sloping-Channel Transistors

“…Figure 2a exhibits the transfer characteristics (I D −V GS ) of our sloping-channel (L CH = 6 nm) WSe 2 FETs by varying temperature (T) from 300 to 77 K. Here, the WSe 2 FET with Al 2 O 3 capping layer showed n-type dominated ambipolar, which can be attributed to positively fixed charges inside the Al 2 O 3 layer and the removal of atmospheric adsorbates on the WSe 2 surface during annealing. 27,28 Threshold voltage (V TH ) of the WSe 2 FETs increases from 2.2 to 3.0 V, as the transfer curves get positively shifted with the increasing T. In the highly ON state, the temperature-independent output current I D at the same of |V GS − V TH | indicates tunneling dominance and ohmic-like contact at the metal/WSe 2 interface of the FETs (Figure 2a). In the OFF state, I D remains constant and low, which results in a high I ON /I OFF ratio (∼1.4 × 10 8 ).…”