Ultrashort Vertical‐Channel van der Waals Semiconductor Transistors

Abstract

Atomically thin 2D van der Waals semiconductors are promising candidates for next‐generation nanoscale field‐effect transistors (FETs). Although large‐area 2D van der Waals materials have been successfully synthesized, such nanometer‐length‐scale devices have not been well demonstrated in 2D van der Waals semiconductors. Here, controllable nanometer‐scale transistors with a channel length of ≈10 nm are fabricated via vertical channels by squeezing an ultrathin insulating spacer between the out‐of‐plane source and drain electrodes, and the feasibility of high‐density and large‐scale fabrication is demonstrated. A large on‐current density of ≈70 µA µm−1 nm−1 at a source–drain voltage of 0.5 V and a high on/off ratio of ≈107–109 are obtained in ultrashort 2D vertical channel FETs with monolayer MoS2 synthesized through chemical vapor deposition. The work provides a promising route toward the complementary metal–oxide–semiconductor‐compatible fabrication of wafer‐scale 2D van der Waals transistors with high‐density integration.

Vertical MoS2 transistors with sub-1-nm gate lengths

“…The iterative progresses of gate length as a function of time line is shown in Fig. 4f 14,[21][22][23][24][25][26][27][28][29][30][31][32][33] . From 2D planar device to 3D FinFET and further GAAFET, the structure of Si transistors gradually changes with better gate control ability.…”

Two dimensional semiconducting materials for ultimately scaled transistors

“…Recently, Young Hee Lee’s group reported 2D vertical FETs by transferring MoS 2 onto the prefabricated source-insulating spacer-drain patterns, in which either the Al 2 O 3 film or h-BN was utilized as the spacer and top-gate dielectric ( Jiang et al., 2020 ). Figure 6 A schematically illustrates the vertical FET structure, in which the effective channel length is defined by the thickness of the Al 2 O 3 /h-BN spacer (∼10 nm, inset of Figure 6 B).…”

“…Inset: schematic illustration of the local enhancement of electric field in 2D vertical FET. Figures A and B are reproduced with permission from ( Jiang et al., 2020 ) Copyright© 2020 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim. (C) Cross-sectional schematic of 2D vertical FET fabricated by using vdW electrodes.…”

DFT Simulation of a Gold Electrode Vapor-Deposition Growth Process and the Effect of Defects on the Electrode Work Function

“…Desai et al fabricated a field-effect transistor (FET), where MoS 2 acts as a channel material, and the effective channel length is only ∼3.9 nm . This work brings us high hope to further make transistors smaller using the 2D semiconducting channel materials. − …”