Ultralow resistance, nonalloyed Ohmic contacts to n-InGaAs

Baraskar, Ashish; Wistey, Mark A.; Jain, Vibhor; Singisetti, Uttam; Burek, Greg J.; Thibeault, B.J.; Lee, Yong Ju; Gossard, A. C.; Rodwell, M.J.W.

doi:10.1116/1.3182737

Cited by 55 publications

(31 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…For higher electron concentration, a shallower depletion at the metalsemiconductor interface exists, thereby decreasing the tunneling resistance and consequently the contact resistivity. We have also observed that an increase in "inactive" dopants keeping the same carrier concentration also reduces contact resistivity (12).…”

Section: B Dopingsupporting

confidence: 55%

Effect of surface preparations on contact resistivity of TiW to highly doped n-InGaAs

Jain

Baraskar

Wistey

et al. 2009

2009 IEEE International Conference on Indium Phosphide &Amp; Related Materials

Self Cite

View full text Add to dashboard Cite

We report the effects of UV-ozone oxidation, oxide removal etch chemistry (dilute HCl or concentrated NH 4 OH), semiconductor doping, and annealing on the contact resistivity ( c ) of Ti 0.1 W 0.9 refractory alloy to ntype InGaAs. The semiconductor surface was oxidized through exposure to UV-ozone, then subsequently etched by either dilute HCl or concentrated NH 4 OH before TiW contacts were deposited by blanket sputtering. InGaAs samples doped at 5 × 10 19 cm -3 , treated with 10 minutes of UV-Ozone then one minute dilute HCl exhibited  c of (1.90 ± 0.35) × 10

show abstract

Section: B Dopingsupporting

confidence: 55%

Effect of surface preparations on contact resistivity of TiW to highly doped n-InGaAs

Jain

Baraskar

Wistey

et al. 2009

2009 IEEE International Conference on Indium Phosphide &Amp; Related Materials

Self Cite

View full text Add to dashboard Cite

show abstract

“…In situ ohmic contacts between Mo/InGaAs without vacuum break are obtained, achieving contact resistivity as low as (1.1 ± 0.6) 9 10 À8 X/cm 2 . 141 By carefully treating the surface with UV-ozone/HCl and atomic H, ex situ ohmic contacts with (1.1 ± 0.6) 9 10 À8 X/cm 2 have also been achieved. 142 The solid solubilities of dopant impurities in III-V semiconductors are always low; thus, we could resort to metal source/drain structures.…”

Section: Group Iii-v Materials Channelsmentioning

confidence: 99%

Mobility Enhancement Technology for Scaling of CMOS Devices: Overview and Status

Song

Zhou

et al. 2011

Journal of Elec Materi

View full text Add to dashboard Cite

The aggressive downscaling of complementary metal-oxide-semiconductor (CMOS) technology to the sub-21-nm technology node is facing great challenges. Innovative technologies such as metal gate/high-k dielectric integration, source/drain engineering, mobility enhancement technology, new device architectures, and enhanced quasiballistic transport channels serve as possible solutions for nanoscaled CMOS. Among them, mobility enhancement technology is one of the most promising solutions for improving device performance. Technologies such as global and process-induced strain technology, hybrid-orientation channels, and new high-mobility channels are thoroughly discussed from the perspective of technological innovation and achievement. Uniaxial strain is superior to biaxial strain in extending metal-oxide-semiconductor field-effect transistor (MOSFET) scaling for various reasons. Typical uniaxial technologies, such as embedded or raised SiGe or SiC source/ drains, Ge pre-amorphization source/drain extension technology, the stress memorization technique (SMT), and tensile or comprehensive capping layers, stress liners, and contact etch-stop layers (CESLs) are discussed in detail. The initial integration of these technologies and the associated reliability issues are also addressed. The hybrid-orientation channel is challenging due to the complicated process flow and the generation of defects. Applying new highmobility channels is an attractive method for increasing carrier mobility; however, it is also challenging due to the introduction of new material systems. New processes with new substrates either based on hybrid orientation or composed of group III-V semiconductors must be simplified, and costs should be reduced. Different mobility enhancement technologies will have to be combined to boost device performance, but they must be compatible with each other. The high mobility offered by mobility enhancement technologies makes these technologies promising and an active area of device research down to the 21-nm technology node and beyond.

show abstract

“…A survey of the growth doping literature suggests that lower growth temperatures improve the dopant activation in growth doped substrates. [51][52][53]121,[123][124][125][126] Fig . 5 plots the reported maximum Si activation in InGaAs as a function of growth temperature from a number of studies.…”

Section: Strategies For Maximizing N-type Dopant Activation In Ingaasmentioning

confidence: 99%

Review—Dopant Selection Considerations and Equilibrium Thermal Processing Limits for n⁺-In_0.53Ga_0.47As

Lind

Aldridge

Hatem

et al. 2016

ECS J. Solid State Sci. Technol.

View full text Add to dashboard Cite

An overview of various processing and dopant considerations for the creation of heavily-doped n-InGaAs is presented. A large body of experimental evidence and theoretical prediction point to dopant vacancy-complexing as the limiting mechanism for electrical activation in heavily Si doped InGaAs and GaAs. Dopant incorporation techniques which require thermal treatment steps to move dopants onto lattice sites like ion implantation and monolayer doping exhibit stable activation up to a limit of ≈1.5 × 1019 cm−3. Growth-based dopant incorporation methods have shown much higher (5 × 1019 cm−3) active concentrations but these activate concentrations are shown in multiple studies to be metastable. Other device specific process-flow constraints with respect to modern CMOS devices which may make some means of dopant incorporation method, or species selection more appropriate for a given application are also discussed.

show abstract

Ultralow resistance, nonalloyed Ohmic contacts to n-InGaAs

Cited by 55 publications

References 11 publications

Effect of surface preparations on contact resistivity of TiW to highly doped n-InGaAs

Effect of surface preparations on contact resistivity of TiW to highly doped n-InGaAs

Mobility Enhancement Technology for Scaling of CMOS Devices: Overview and Status

Review—Dopant Selection Considerations and Equilibrium Thermal Processing Limits for n⁺-In_0.53Ga_0.47As

Contact Info

Product

Resources

About

Ultralow resistance, nonalloyed Ohmic contacts to n-InGaAs

Cited by 55 publications

References 11 publications

Effect of surface preparations on contact resistivity of TiW to highly doped n-InGaAs

Effect of surface preparations on contact resistivity of TiW to highly doped n-InGaAs

Mobility Enhancement Technology for Scaling of CMOS Devices: Overview and Status

Review—Dopant Selection Considerations and Equilibrium Thermal Processing Limits for n+-In0.53Ga0.47As

Contact Info

Product

Resources

About

Review—Dopant Selection Considerations and Equilibrium Thermal Processing Limits for n⁺-In_0.53Ga_0.47As