Ultra Wideband Receiver Protection Limiter Using 0.13m pHEMT Technology

Chaturvedi, Sandeep; Badnikar, S.L.; Naik, Anant A.

doi:10.1109/imarc.2017.8449717

Cited by 3 publications

(2 citation statements)

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“…However, as the first block of the transceiver, the LNAs are the most vulnerable to the high power input signals, which are present due to the leakage from the transmitter output or some other high power transmitters. 1 Especially in radar systems, the transmitting and receiving frequencies are close to each other; the excessive power is usually fed by unintentional reflections of the power from the transmission path. Limiters are usually employed in the front-end module to protect active devices in the LNAs, which also should have a minimum insertion loss so as to assure the receiver's sensitivity in the receiving period simultaneously.…”

Section: Introductionmentioning

confidence: 99%

“…The low noise amplifier (LNA) is one of the key components in receiver architectures, which is used to receive the radiofrequency (RF) signal. However, as the first block of the transceiver, the LNAs are the most vulnerable to the high power input signals, which are present due to the leakage from the transmitter output or some other high power transmitters 1 …”

Section: Introductionmentioning

confidence: 99%

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A compact Ka‐band limiter‐low noise amplifier MMIC with high power capability

Yang

Zhang

Wang

et al. 2022

Micro & Optical Tech Letters

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This paper presents a 30–36 GHz limiter low‐noise amplifier (limiter‐LNA) MMIC for high power and high mobility millimeter‐wave radar systems. The PIN‐diode limiter network and the LNA are codesigned to realize high input‐power handling capability, good small‐signal performance, and small chip area. A two‐state matching capacitor is presented to improve both the input‐power handling capability at the high input‐power level and the input return loss at the small‐signal level. The proposed circuit is fabricated with a combined PIN/0.15‐µm‐GaAs‐pHEMT process. The limiter‐LNA is capable of handling 39 dBm continuous wave (CW) input‐power without failure with only two limiter stages. The measured noise figure is 1.8–2.5 dB, the small‐signal gain is 18.5 ± 0.5 dB, the output power at 1 dB compression point is larger than 11 dBm, and the dc power consumption is 72 mW. The chip area, including testing pads, is only 2.1 mm × 1.0 mm. This limiter‐LNA MMIC is believed to have the highest input‐power handling capability and smallest chip area among limiter‐LNA MMICs at this frequency range reported up to date.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%