Ultra Thin Hermetic Wafer level, Chip Scale Package

Shiv, Lior; Heschel, M.; Korth, H.; Weichel, S.; Hauffe, R.; Kilian, A.; Semak, B.; Houlberg, M.; Egginton, P.; Hase, A.; Kuhmann, Jochen Friedrich

doi:10.1109/ectc.2006.1645794

Cited by 5 publications

(4 citation statements)

References 5 publications

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“…Fig. 25 shows a SOI-based WLCSP process developed for MEMS applications, so called HyCap [236]. The tapered TSVs only go through the device layer of the SOI wafer.…”

Section: Wlcspmentioning

confidence: 99%

3-D Integration and Through-Silicon Vias in MEMS and Microsensors

Wang

2015

J. Microelectromech. Syst.

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After two decades of intensive development, 3-D integration has proven invaluable for allowing integrated circuits to adhere to Moore's Law without needing to continuously shrink feature sizes. The 3-D integration is also an enabling technology for hetero-integration of microelectromechanical systems (MEMS)/microsensors with different technologies, such as CMOS and optoelectronics. This 3-D heterointegration allows for the development of highly integrated multifunctional microsystems with small footprints, low cost, and high performance demanded by emerging applications. This paper reviews the following aspects of the MEMS/ microsensor-centered 3-D integration: fabrication technologies and processes, processing considerations and strategies for 3-D integration, integrated device configurations and wafer-level packaging, and applications and commercial MEMS/ microsensor products using 3-D integration technologies. Of particular interest throughout this paper is the heterointegration of the MEMS and CMOS technologies. [2015-0158]Index Terms-Three-dimensional (3-D) integration, microelectromechanical systems (MEMS), microsensor, packaging, hetero-integration, interposer, through-silicon-via (TSV), waferlevel packaging, microsystem.

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“…Fig. 25 shows a SOI-based WLCSP process developed for MEMS applications, so called HyCap [236]. The tapered TSVs only go through the device layer of the SOI wafer.…”

Section: Wlcspmentioning

confidence: 99%

3-D Integration and Through-Silicon Vias in MEMS and Microsensors

Wang

2015

J. Microelectromech. Syst.

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“…Some people attribute these voids to tin oxide, contaminations or to Kirkendall voids due to inter-metallic formation [4], and solve the problem with a plasma surface activation before bonding [6], an aging of samples at 200°C or an active atmosphere during reflow [4][5] [7]. Voids also come from the pores in the AuSn ECD process.…”

Section: Studymentioning

confidence: 99%

“…In these cases, 3 to 5/lm-thick solder joints are fabricated by PVD and lift-off processes. ECD is also reported, but rather for flip-chip die attach [4], and not often for wafer-to-wafer bonding [7]. An ECD process, which is a lower cost approach than PVD, has been developed.…”

Section: Introductionmentioning

confidence: 98%

Hermetic wafer-level packaging development for RF MEMS switch

Ferrandon

Greco

Lagoutte

et al. 2010

3rd Electronics System Integration Technology Conference ESTC

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This paper presents a low temperature «350°C) hermetic solution to fully package at wafer level a RF MEMS switch connecting upwards. The switch has a piezoelectric actuation and an electrostatic hold. In this architecture, the packaging is actually part of the switch itself and shall meet many requirements:• Use of Thru-Silicon Via (TSV) for DC and RF connections with minimum via resistance • Electrical connection between both wafers • Hermetic sealing under controlled atmosphere with 5 +1-0.5 /lm gap between the switch and the cap wafers • No degradation of the switch performances • Low temperature «350°C) packaging process to preserve the moving part materials • Electrode and dielectric for electrostatic hold • No sticking of the moving contact Two main processes were developed and implemented together: Au-Sn eutectic bonding under atmospheric pressure with 5/lm spacers to ensure the gap, and 'post-bonding' TSV. The complete process flow of the cap wafer, bonding and TSV process is presented. The solder material, made of 80wt.%Au and 20wt.%Sn, is only 5/lm thick and is electroplated. SEM, XPS, EDX analyses and shear tests have been performed. Hermeticity evaluation tests have been set-up, and a standard leak rate lower than 1.2 x 10-1 2 mbar.lls has been demonstrated using the membrane de flexion method. TSV and Au-Sn bump resistance is less than I4mn and IOmn with a yield of 92% and 98% respectively across the 200mm wafer. The resistance between 2 via is more than 500Mn at 5V. As to the packaged switch, its insertion losses at 2 GHz are 0.74dB and its off-state isolation is 43.6dB. At last, it has been demonstrated that the substrates resistivity has a great influence on the insertion losses. IntroductionTargeting the mobile communication market, a RF MEMS piezoelectric switch connecting upwards with low-voltage actuation and electrostatic hold has been developed [1] (Figure 1). Indeed, RF MEMS switches compared to semiconductor switches are known for their potential great performances at the GHz frequency range such as lower insertion losses, better isolation and better cut-off frequency.Piezoelectric actuation is a good means to have low operation voltage, and electrostatic hold enables strong pressure on the contact, producing low contact resistance and low RF losses. PZT has been selected for its high piezoelectric constants. Requiring a 5/lm gap enables

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“…The reported Si caps realized with this approach were relatively thick, ranging from 60 µm to 80 µm [37]- [40]. Besides, either wide metal sealing rings of 75-100 µm were used [39], [40], or no details of the package design, sealing process, and resulting long-term hermeticity are described in the literature reports [37], [38].…”

mentioning

confidence: 99%

Wafer-Level Vacuum Sealing by Transfer Bonding of Silicon Caps for Small Footprint and Ultra-Thin MEMS Packages

Wang

Bleiker

Edinger

et al. 2019

J. Microelectromech. Syst.

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Vacuum and hermetic packaging is a critical requirement for optimal performance of many micro-electromechanical systems (MEMS), vacuum electronics, and quantum devices. However, existing packaging solutions are either elaborate to implement or rely on bulky caps and footprint-consuming seals. Here, we address this problem by demonstrating a waferlevel vacuum packaging method featuring transfer bonding of 25-µm-thin silicon (Si) caps that are transferred from a 100-mm-diameter silicon-on-insulator (SOI) wafer to a cavity wafer to seal the cavities by gold-aluminum (Au-Al) thermocompression bonding at a low temperature of 250 • C. The resulting wafer-scale sealing yields after wafer dicing are 98% and 100% with sealing rings as narrow as 6 and 9 µm, respectively. Despite the small sealing footprint, the Si caps with 9-µm-wide sealing rings demonstrate a high mean shear strength of 127 MPa. The vacuum levels in the getter-free sealed cavities are measured by residual gas analysis to be as low as 1.3 mbar, based on which a leak rate smaller than 2.8 × 10 −14 mbarL/s is derived. We also show that the thickness of the Si caps can be reduced to 6 µm by post-transfer etching while still maintaining excellent hermeticity. The demonstrated ultra-thin packages can potentially be placed in between the solder bumps in flip-chip interfaces, thereby avoiding the need of through-capvias in conventional MEMS packages. [2018-0257] Index Terms-Vacuum, hermetic, packaging, sealing, MEMS, ultra-thin package, small footprint, transfer bonding, 3D integration, flip chip, aluminum, gold, thermo-compression bonding. I. INTRODUCTION V ACUUM packaging is a process for encapsulating a device (e.g. a MEMS or nano-electro-mechanical system (NEMS) device) in a vacuum environment and maintaining the internal vacuum level using hermetic seals. It enables functionality and long-term reliability of various MEMS devices, such as inertial sensors, pressure sensors and infrared detectors, but typically also constitutes a significant part of their cost in high-volume production [1], [2]. As a general trend,

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Ultra Thin Hermetic Wafer level, Chip Scale Package

Cited by 5 publications

References 5 publications

3-D Integration and Through-Silicon Vias in MEMS and Microsensors

3-D Integration and Through-Silicon Vias in MEMS and Microsensors

Hermetic wafer-level packaging development for RF MEMS switch

Wafer-Level Vacuum Sealing by Transfer Bonding of Silicon Caps for Small Footprint and Ultra-Thin MEMS Packages

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