1999
DOI: 10.1143/jjap.38.2393
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Ultra-Low Resistance, Through-Wafer Via (TWV) Technology and Its Applications in Three Dimensional Structures on Silicon

Abstract: This paper presents an ultra-low resistance, high wiring density, through-wafer via (TWV) technology that is compatible with standard silicon wafer processing. Vias as small as 30 µm by 30 µm are fabricated through a 525 µm thick wafer. This results in an aspect ratio for the via that is greater than 17:1. Furthermore, the dc resistance of a single via is less than 50 mΩ. Key fabrication steps, including the silicon dry etch, copper metallization, and photoresist electroplating, are des… Show more

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Cited by 42 publications
(22 citation statements)
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“…Previous DRIE-via technologies use a thin coating of metal to line the inside surface of the via [9], [10], whereas others fill the via with highly doped polysilicon to achieve a low-impedance interconnect [11]. These different via technologies have found applications in three-dimensional (3-D) chip stacks [5], as a substrate coil inductor [9], microstrip substrate interconnect [10], and in MEMS [7], [11].…”
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confidence: 99%
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“…Previous DRIE-via technologies use a thin coating of metal to line the inside surface of the via [9], [10], whereas others fill the via with highly doped polysilicon to achieve a low-impedance interconnect [11]. These different via technologies have found applications in three-dimensional (3-D) chip stacks [5], as a substrate coil inductor [9], microstrip substrate interconnect [10], and in MEMS [7], [11].…”
mentioning
confidence: 99%
“…These different via technologies have found applications in three-dimensional (3-D) chip stacks [5], as a substrate coil inductor [9], microstrip substrate interconnect [10], and in MEMS [7], [11]. The novelty of our via technology is that it features an insulator liner and a solid metal core.…”
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confidence: 99%
“…Through wafer interconnects (TWIs) have distinct advantages to other advanced 3-D packaging schemes [9]. Additional miniaturization, increased interconnection density, and higher performance are possible by stacking die with TWIs [10].…”
mentioning
confidence: 99%
“…In addition, the capacitance between the ground and the metal on the cavity sidewalls prevents it from being used in high-frequency applications. Deep-reactive ion etching (DRIE) is another option for TWV fabrication [5], [11]- [20]. DRIE is capable of etching vertical high-aspect ratio holes; however, the maximum available aspect ratio of DRIE limits the diameter of TWVs etched on whole-thickness standard 4-in wafers larger than 20 m. Chemical mechanical polishing (CMP) facilitates DRIE etching of small TWVs by thinning wafers [14]- [16], and TWVs with diameters as small as 10 m have been obtained by DRIE etching silicon wafers from both sides.…”
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confidence: 99%
“…Currently, copper electrochemical deposition techniques are utilized increasingly in fabrication of interconnects [25] because of the compatibility of copper with conventional multilayer interconnection in large-scale integration, the high conductivity, and the low cost of physical or chemical vapor depositions. Electrochemical deposition of copper into holes and trenches lined with copper seed layer and diffusion barrier has demonstrated good via-filling capability and low resistivity (less than cm) [5], [11]- [16]. Heavily doped poly-silicon [17]- [20] has also been used to fill TWVs due to its IC compatibility, though its electrical features are not as good as metals.…”
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confidence: 99%