Ultra-Low Resistance, Through-Wafer Via (TWV) Technology  and Its Applications in Three Dimensional Structures on Silicon

Soh, H. Tom; Yue, C. Patrick; McCarthy, A.M.; Ryu, Chunghyun; Lee, Thomas H.; Wong, Sai‐Keung; Quate, C. F.

doi:10.1143/jjap.38.2393

Cited by 42 publications

(22 citation statements)

References 5 publications

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“…Previous DRIE-via technologies use a thin coating of metal to line the inside surface of the via [9], [10], whereas others fill the via with highly doped polysilicon to achieve a low-impedance interconnect [11]. These different via technologies have found applications in three-dimensional (3-D) chip stacks [5], as a substrate coil inductor [9], microstrip substrate interconnect [10], and in MEMS [7], [11].…”

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confidence: 99%

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A Through-Wafer Interconnect in Silicon for RFICs

Scholvin

Alamo

2004

IEEE Trans. Electron Devices

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Abstract-In order to minimize ground inductance in RFICs, we have developed a high-aspect ratio, through-wafer interconnect (or substrate via) in silicon that features a silicon nitride barrier liner and completely filled Cu core. We have fabricated vias with a nominal aspect ratio of 30 and verified the integrity of the insulating liner in vias with an aspect ratio of eight. The inductance of vias with nominal aspect ratios between three and 30 approach the theoretically expected values. This interconnect technology was exploited in a novel Faraday cage structure for substrate crosstalk suppression in system-on-chip applications. The isolation structure consists of a ring of grounded vias that surrounds sensitive or noisy portions of a chip. This Faraday cage structure has shown noise suppression of 30 dB at 10 GHz and 16 dB at 50 GHz at a distance of 100 m when compared to the reference structure.Index Terms-Ground inductance, Si RF technology, substrate noise, substrate via, system-on-chip (SOC), three-dimensional interconnects, through-wafer interconnect.

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confidence: 99%

“…These different via technologies have found applications in three-dimensional (3-D) chip stacks [5], as a substrate coil inductor [9], microstrip substrate interconnect [10], and in MEMS [7], [11]. The novelty of our via technology is that it features an insulator liner and a solid metal core.…”

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confidence: 99%

A Through-Wafer Interconnect in Silicon for RFICs

Scholvin

Alamo

2004

IEEE Trans. Electron Devices

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“…Through wafer interconnects (TWIs) have distinct advantages to other advanced 3-D packaging schemes [9]. Additional miniaturization, increased interconnection density, and higher performance are possible by stacking die with TWIs [10].…”

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Integrating Through-Wafer Interconnects With Active Devices and Circuits

Jozwiak

Southwick

Johnson

et al. 2008

IEEE Trans. Adv. Packag.

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Abstract-Through wafer interconnects (TWIs) enable vertical stacking of integrated circuit chips in a single package. A complete process to fabricate TWIs has been developed and demonstrated using blank test wafers. The next step in integrating this technology into 3-D microelectronic packaging is the demonstration of TWIs on wafers with preexisting microcircuitry. The circuitry must be electrically accessible from the backside of the wafer utilizing the TWIs; the electrical performance of the circuitry must be unchanged as a result of the TWI processing; and the processing must be as cost effective as possible. With these three goals in mind, several options for creating TWIs were considered. This paper explores the various processing options and describes in detail, the final process flow that was selected for testing, the accompanying masks that were designed, the actual processing of the wafers, and the electrical test results.

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“…In addition, the capacitance between the ground and the metal on the cavity sidewalls prevents it from being used in high-frequency applications. Deep-reactive ion etching (DRIE) is another option for TWV fabrication [5], [11]- [20]. DRIE is capable of etching vertical high-aspect ratio holes; however, the maximum available aspect ratio of DRIE limits the diameter of TWVs etched on whole-thickness standard 4-in wafers larger than 20 m. Chemical mechanical polishing (CMP) facilitates DRIE etching of small TWVs by thinning wafers [14]- [16], and TWVs with diameters as small as 10 m have been obtained by DRIE etching silicon wafers from both sides.…”

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“…Currently, copper electrochemical deposition techniques are utilized increasingly in fabrication of interconnects [25] because of the compatibility of copper with conventional multilayer interconnection in large-scale integration, the high conductivity, and the low cost of physical or chemical vapor depositions. Electrochemical deposition of copper into holes and trenches lined with copper seed layer and diffusion barrier has demonstrated good via-filling capability and low resistivity (less than cm) [5], [11]- [16]. Heavily doped poly-silicon [17]- [20] has also been used to fill TWVs due to its IC compatibility, though its electrical features are not as good as metals.…”

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confidence: 99%

Silicon Micromachining of High Aspect Ratio, High-Density Through-Wafer Electrical Interconnects for 3-D Multichip Packaging

Wang

Nguyen

et al. 2006

IEEE Trans. Adv. Packag.

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Abstract-This paper presents a novel silicon micromachining method, which combines tetra methyl ammonium hydroxide (TMAH) etching and deep-reactive ion etching (DRIE) along with bottom-up copper electroplating, to fabricate high-density and high-aspect ratio through-wafer electrical interconnects (TWEIs) for three-dimensional multichip packaging. The silicon wafer was locally etched with TMAH from the backside until the desired membrane thickness was reached, and then DRIE was performed on the membrane until the holes were etched through. TMAH etching preserved large areas of the wafers at the original thickness, thus, ensuring relatively strong mechanical strength and manipulability. DRIE made it possible to realize high-aspect ratio holes with minimized wafer area consumption. A new bottom-up copper electroplating technique was developed to fill the high-aspect ratio through-wafer holes. This method can avoid seams and voids while achieving attractive electrical features. Through-wafer holes, as small as 5 m in diameter, have been realized by using the combination of TMAH and DRIE, and have been completely and uniformly filled by using bottom-up copper electroplating.Index Terms-Copper electroplating, deep-reactive ion etching (DRIE), interconnect, packaging, through-wafer, tetra methyl ammonium hydroxide (TMAH).

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Ultra-Low Resistance, Through-Wafer Via (TWV) Technology and Its Applications in Three Dimensional Structures on Silicon

Cited by 42 publications

References 5 publications

A Through-Wafer Interconnect in Silicon for RFICs

A Through-Wafer Interconnect in Silicon for RFICs

Integrating Through-Wafer Interconnects With Active Devices and Circuits

Silicon Micromachining of High Aspect Ratio, High-Density Through-Wafer Electrical Interconnects for 3-D Multichip Packaging

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