Ultra low power capless LDO with dynamic biasing of derivative feedback

Esteves, José; Pereira, João Baptista Borges; Paisana, J.; Santos, M.B.

doi:10.1016/j.mejo.2012.10.010

Cited by 11 publications

(5 citation statements)

References 15 publications

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“…Additionally, the marginal F.O.M. 1 improvement over [4] is achieved by using a more cost effective CMOS technology (0.35 mm over 0.13 mm) with doubled I outðmaxÞ . However, F.O.M 1, 2 of [16] is lower than the proposed design.…”

Section: Post-layout Simulation Resultsmentioning

confidence: 99%

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A low-power fast transient output capacitor-free adaptively biased LDO based on slew rate enhancement for SoC applications

Lim

Lai

Tan

et al. 2015

Microelectronics Journal

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Section: Post-layout Simulation Resultsmentioning

confidence: 99%

“…Low-dropout regulators (LDOs) are one of the most essential module in modern power management integrated circuits (PMICs), supplying clean and ideally ripple-free supply voltage to noise sensitive blocks such as analogue, mixed-signals or radiofrequency circuit blocks [1][2][3][4]. As illustrated in Fig.…”

Section: Introductionmentioning

confidence: 99%

A low-power fast transient output capacitor-free adaptively biased LDO based on slew rate enhancement for SoC applications

Lim

Lai

Tan

et al. 2015

Microelectronics Journal

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“…However, when only active area is considered, this value is reduced to 468µm 2 . Furthermore, the voltage difference (ΔVout) of the proposed LDO is lower than that of [21]- [22], [14]- [17], and [19]- [20], but it is higher than that of [15].…”

Section: Post Layout Performance Characterizationmentioning

confidence: 93%

“…Particularly, the optimization of the power dissipated in these circuits is the subject of study for many designers. The classics regulators CMOS operating in the strong inversion region [22]- [23], the design of these circuits is made with polarized transistors in the region of strong inversion of the drain-source channel [22]. In this region, the gatesource polarization voltage VGS is greater than the conduction threshold voltage VTH (│VGS│> │VTH│) hence the drain current of a few microamperes and therefore the power dissipated in the regulator is a few microwatts.…”

Section: Introductionmentioning

confidence: 99%

Nano-Power Low-Dropout Voltage Regulator Circuit in 90-nm CMOS Technology for RF SoC Applications

Akhamal

Chakir

Ameziane

et al. 2021

Wseas Transactions on Power Systems

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This paper presents a nano-power Low Drop-Out (LDO) voltage regulator circuit for Radio-Frequency System-on-Chip (RF SoC) applications, this LDO is designed for a smaller dimension due to CMOS technology and in the weak inversion region, can thus be used to minimize power loss of LDO regulator without transientresponse degradation. The proposed structure its low power dissipation make it ideal for RF system-on-chip applications that require low power dissipation under different loading conditions. In order to optimize performance for LDO, the proposed amplifier helps to minimize power of LDO regulators without using any onchip and off-chip compensation capacitors. The output spot noise at 100Hz and 1 kHz are 200nV/sqrt (Hz) and 6nV/sqrt (Hz), respectively. The active area of the circuit is 850 µm2 . The regulator operates with supply voltages from 1.2V to 2V.

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“…An LDO regulator is basically a negative feedback system in which the resistivity of the pass device is controlled by an error amplifier such that a constant voltage difference is maintained between input and output terminals even though there are fluctuations in supply voltage and load demand [1][2][3]. The vital performance indicators of LDO regulators are line and load regulation, maximum load current, transient response, on-chip capacitance value, stability, quiescent current magnitude, and power supply rejection ratio [PSRR] [4,5].…”

Section: Introductionmentioning

confidence: 99%

A low dropout voltage regulator with a transient voltage spikes reducer and improved figure of merit

Prasad¹,

Shama

2020

Turk J Elec Eng & Comp Sci

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An area efficient output capacitor-free low dropout [LDO] voltage regulator with an improved figure of merit is presented in this paper. The proposed LDO regulator consists of a novel, dynamically biased error amplifier that reduces overshoot and undershoot voltage spikes arising from abrupt load changes. Source bulk modulation is employed to enhance the current driving capability of the pass transistor. An adaptive biasing scheme is also used along with dynamic biasing to improve the current efficiency of the system. The on-chip capacitor required for proper working of the LDO regulator is only 35 pF. The proposed LDO regulator is designed and simulated in 180 nm standard CMOS technology. The LDO regulator exhibits a line regulation of 1.67 mV / V and a load regulation of 100 µV / mA. When load changes from 0 mA to 100 mA in 1 µ s, an undershoot of 148 mV and an overshoot of 172 mV are observed. The measured power supply rejection ratio is 25 dB at 100 kHz. The working of the proposed LDO regulator has been tested under all process corners and Monte-Carlo statistical analysis reveals that it is robust against process variations and local mismatch.

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Ultra low power capless LDO with dynamic biasing of derivative feedback

Cited by 11 publications

References 15 publications

A low-power fast transient output capacitor-free adaptively biased LDO based on slew rate enhancement for SoC applications

A low-power fast transient output capacitor-free adaptively biased LDO based on slew rate enhancement for SoC applications

Nano-Power Low-Dropout Voltage Regulator Circuit in 90-nm CMOS Technology for RF SoC Applications

A low dropout voltage regulator with a transient voltage spikes reducer and improved figure of merit

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