Ultra-Low Power 18-Transistor Fully Static Contention-Free Single-Phase Clocked Flip-Flop in 65-nm CMOS

Cai, Yunpeng; Savanth, Anand; Prabhat, Pranay; Myers, James; Weddell, Alex S.; Kázmierski, Tom J.

doi:10.1109/jssc.2018.2875089

Cited by 61 publications

(38 citation statements)

References 20 publications

(30 reference statements)

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“…From Equation ( 4), CL dictates load capacitance of the latch at output node Q, VDD dictates the supply voltage of the latch and f dictates the frequency of operation for the latch. [10], [19]. It also dictates that as the technology scales down the parameters like power, latency & figure of merit also scale down respectively.…”

Section: Resultsmentioning

confidence: 99%

Design and Analysis of FS-TSPC-DET Flip-Flop for IoT Applications

Prabhakar¹,

Naresh²,

Krishna³

et al. 2021

TURCOMAT

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The paper outlines the utmost importance of energy-efficient devices for IoT applications and recommends adual edge-triggeredTSPC flip-flop in fully-static mode at 45nm technology with low supply rail carried out in CMOS using MENTOR GRAPHICS tool.The proposed flip-flop proved to be energy efficient compared to traditional double and single edge-triggered flip-flops in terms of latency, power, the figure of merit and area for IoT applications. A comparison of two types of dual-edge triggered flip-flops are analyzed concerning the mentioned performance metrics and deduces the best flip-flop for IoT applications. Clock overlap issues are turning down in dual edge-triggered TSPC flip-flopcompared with a conventional dual edge-triggered flip-flop in full static modeand allow stringent operation at 1V supply rail thatdelivers1.14uW power, 0.60fJ figure of merit and 531.99ps latency at 45nm CMOS

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Section: Resultsmentioning

confidence: 99%

Design and Analysis of FS-TSPC-DET Flip-Flop for IoT Applications

Prabhakar¹,

Naresh²,

Krishna³

et al. 2021

TURCOMAT

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“…Pulse-Triggered Flip-Flop (PFF) is an option to help in penalty reducing or area diminishing due to its simple and compact structure [17,18]. However, high power consumption due to redundant switching activities and contention mechanism is usually an issue [14,19,20,21].…”

Section: Introductionmentioning

confidence: 99%

A low power consumption and cost-efficient SEU-tolerant pulse-triggered flip-flop design

Jin

Zhang

et al. 2021

IEICE Electron. Express

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A power-efficient Single Event Upset (SEU) -tolerant pulsetriggered flip-flop design is presented. The dual-modular redundant design takes advantage of concise formation of pulse-triggered designs, and avoids the disadvantages of it, such as high power consumption. Clock-gating scheme is applied to reduce power consumption. The static configuration and the avoidance of contention mechanism led to the balance of power consumption, speed and SEU tolerance. The SEU tolerance is evaluated by means of SEU cross section, which is significantly lower than conventional D flip-flop. The proposed flip-flop is designed in 55nm CMOS technology to evaluate performances. The proposed design achieves the lowest power consumption, which is even lower than conventional D flip-flop. Although the speed is sacrificed, the lowest power-delay product is achieved among hardened designs. The proposed design provides solution to speedinsensitive and power-constrained applications.

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“…Therefore, reducing flip-flop's power consumption has significant impact on whole system's energy efficiency. Many different types of flip-flops with unique topologies have been studied for achieving better efficiency of flip-flops and processors [3,4,5,6,7].…”

Section: Introductionmentioning

confidence: 99%

A PVT variation-tolerant static single-phase clocked dual-edge triggered flip-flop for aggressive voltage scaling

Lee

2019

IEICE Electron. Express

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A novel static single-phase clocked (SSPC) dual-edge triggered flip-flop (DET-FF) is proposed to allow energy-efficient operation with aggressive voltage scaling. By employing two static latches with a singlephase clock, contention and clock phase mismatch is avoided, which significantly improves tolerance to PVT variations. The post-layout simulation performed with 28 nm CMOS technology shows that the proposed SSPC DET-FF consumes less power and has significantly better powerperformance trade off (PDP) than prior-art DET-FFs. Our Monte Carlo analysis also showed that its supply voltage can be aggressively scaled down to 0.3 V even with PVT variations.

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Ultra-Low Power 18-Transistor Fully Static Contention-Free Single-Phase Clocked Flip-Flop in 65-nm CMOS

Cited by 61 publications

References 20 publications

Design and Analysis of FS-TSPC-DET Flip-Flop for IoT Applications

Design and Analysis of FS-TSPC-DET Flip-Flop for IoT Applications

A low power consumption and cost-efficient SEU-tolerant pulse-triggered flip-flop design

A PVT variation-tolerant static single-phase clocked dual-edge triggered flip-flop for aggressive voltage scaling

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