Ultra low-EOT (5 Å) gate-first and gate-last high performance CMOS achieved by gate-electrode optimization

BTI reliability of ultra-thin EOT MOSFETs for sub-threshold logic

“…The EOT was aggressively scaled by means of IL reduction through an oxygen-scavenging technique. Further details on the process can be found elsewhere [1].…”

“…This results in a higher oxide capacitance (C ox ) which allows for better electrostatic control and enhanced current drive. Several groups have already demonstrated functional devices with Ultra-Thin Equivalent Oxide Thickness (UT-EOT) down to $5 Å [1,2]. However, due to the ever increasing oxide electric field (E ox ), the reliability issue is becoming a show stopper.…”

Investigation of Low‐Frequency Noise Characterization of 28‐nm High‐k pMOSFET with Embedded SiGe Source/Drain

“…A total of 20 atomic layer deposition cycles for HfO 2 were deposited on the top of the SiO 2 interfacial layer, and the thickness of all gate stacks was approximately 1.6∼1.7 nm. A thin TiN layer was deposited on HfO 2 layer as a capping layer for selective removal of the dummy poly-Si gate [15]. After the S/D activation is annealed, the dummy poly-Si gate was removed and then other metals were deposited to tune the work function and achieve the idea value (5.0∼5.2) [16].…”

Improved NBTI reliability with sub-1-nanometer EOT ZrO2 gate dielectric compared with HfO2

“…Manuscript pMOSFET devices are fabricated on 300-mm (100) Si-wafers using HfO 2 , ZrO 2 , or HfZrO (50% of Zr) dielectrics by an atomic layer deposition technique. In particular, sub-1-nanometer equivalent oxide thickness (EOT) is obtained by adopting a thinner TiN metal gate inducing Si in-diffusion and reducing the interfacial oxide layer thickness [10]. The initial interface SiO 2 thickness is ∼0.8 nm, but expected to be 0-0.4 nm after thin TiN metal adoption.…”