2012
DOI: 10.1063/1.4746762
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Ultra high density three dimensional capacitors based on Si nanowires array grown on a metal layer

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Cited by 25 publications
(18 citation statements)
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“…Routes to increase the capacitance density of solid‐state microcapacitors include the increase in the dielectric permittivity of the insulator (use of high‐ k dielectrics), the decrease in the oxide thickness, and the increase in microcapacitor surface area. One way to increase the effective electrode area without increasing the footprint area of the device is by 3D nanostructuring of the electrodes . Another approach reported in the literature is the use of stacks of MIM capacitors on a 3D‐structured Si substrate as a means to increase the total capacitance areal density …”
Section: On‐chip Microcapacitors For Energy Storagementioning
confidence: 99%
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“…Routes to increase the capacitance density of solid‐state microcapacitors include the increase in the dielectric permittivity of the insulator (use of high‐ k dielectrics), the decrease in the oxide thickness, and the increase in microcapacitor surface area. One way to increase the effective electrode area without increasing the footprint area of the device is by 3D nanostructuring of the electrodes . Another approach reported in the literature is the use of stacks of MIM capacitors on a 3D‐structured Si substrate as a means to increase the total capacitance areal density …”
Section: On‐chip Microcapacitors For Energy Storagementioning
confidence: 99%
“…They are both based on the parallel‐plate capacitor configuration with 3D‐structured electrodes. In the first approach, shown in Figure a, a 3D‐structured substrate is used which is either a semiconductor or a metal, on which the dielectric and top electrode are deposited, following its morphology . The capacitors have thus either the MIS or MIM configuration.…”
Section: On‐chip Microcapacitors For Energy Storagementioning
confidence: 99%
“…We studied an industrially relevant metal/substrate combination, Cu on TiN, as TiN is known to be an efficient diffusion barrier widely used in Cu interconnections in Si chips. We further investigated the use of these nanoparticles in Si nanowires (SiNWs) growth in CMOS compatible conditions (< 450 °C), as they are promising building blocks for nanoscaled microelectronic devices, for instance to prepare high surface area capacitors in interconnections . SiNWs were grown by Catalytic Chemical Vapor Deposition (C‐CVD) using the Vapor‐Solid‐Solid mechanism, in which a metallic nanoparticle acts as a catalyst for Si precursor decomposition, as well as a template for nanowire formation, the nanoparticle diameter controlling the nanowire diameter …”
Section: Introductionmentioning
confidence: 99%
“…Therefore, 3D nanocapacitor arrays with a high aspect ratio are considered to be a robust candidate to achieve a high capacitance density. To date, many methods have been proposed for the fabrication of 3D nanocapacitors, mainly focusing on different nanostructured templates such as anodic aluminum oxide (AAO) [ 5 11 ], carbon nanotubes (CNTs) [ 12 , 13 ], silicon-based nanowires, nanoholes and nanopillars [ 14 18 ], and InAs nanowires [ 19 ]. The AAO template has been widely used because nanopore arrays exhibit a high degree of regularity and uniformity.…”
Section: Introductionmentioning
confidence: 99%