Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs

Matsutani, Hiroki; Koibuchi, Michihiro; Ikebuchi, Daisuke; Usami, Kimiyoshi; Nakamura, Hiroshi; Amano, Hideharu

doi:10.1109/nocs.2010.16

Cited by 62 publications

(59 citation statements)

References 18 publications

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“…Matsutani et al present run-time power gating for network routers in several publications [13], [14]. But besides a not negligible resource overhead, additional computation overhead is necessary inside the router to produce the information required to generate a wake-up request signal.…”

Section: IImentioning

confidence: 99%

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Network on Chip Router with Power Management Unit for Improved Network Fabric Power Efficiency

2017

IJRTER

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Abstract-Growing chip integration density and increasing frequencies lead to tremendous leakage power and henceforth to chip heat problems. Power management is one possibility to reduce the power consumption and get the temperature problem under control. Current technology mainly focuses on power-gating techniques on basis of multi-core systems but leaving the network perspective out of scope. We provide a holistic concept, bringing together voltage and frequency scaling techniques for network-on-chips. Following this, network static power consumption could be minimized without affecting the system performance. We present a light-weight power management controller for network-on-chips with online monitoring to optimize the power consumption of network resources. Our work comprises a hardware simulation model for design space exploration of varying technology specific parameters and an FPGA based prototype for verification. The power saving poten-tial heavily depend on the network communication load.

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Section: IImentioning

confidence: 99%

“…Matsutani et al [13] introduced a look-ahead sleep control to reduce the performance penalty. In contrast, our approach can achieve the same results without additional resources.…”

Section: Power Analysismentioning

confidence: 99%

Network on Chip Router with Power Management Unit for Improved Network Fabric Power Efficiency

2017

IJRTER

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“…There are also studies which focus on improving the bandwidth of NoCs through different approaches, such as compression [9], [10], allocators with higher matching efficiency [8], and different buffer designs allowing higher capacity [7]. Power-wise, there are many existing studies on saving the static power of routers through power management techniques such as PG [11] or proportionally supplying power to the network based on traffic demand [14]. Each one of these optimization techniques can be very useful towards their purposes but up to this point, there is no such work which tries to look at multiple optimization techniques for NoCs.…”

Section: Related Workmentioning

confidence: 99%

“…PG has been applied to different types of circuit blocks with various granularities. Applying it to routers in NoCs can help the routers to save their static power when they are not actively used [11]. As stated in Eq.…”

Section: The Noc Optimization Techniques and Their Impactsmentioning

confidence: 99%

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A Runtime Optimization Selection Framework to Realize Energy Efficient Networks-on-Chip

Kondo

Nakada

et al. 2016

IEICE Trans. Inf. & Syst.

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SUMMARYNetworks-on-Chip (or NoCs, for short) play important roles in modern and future multi-core processors as they are highly related to both performance and power consumption of the entire chip. Up to date, many optimization techniques have been developed to improve NoC's bandwidth, latency and power consumption. But a clear answer to how energy efficiency is affected with these optimization techniques is yet to be found since each of these optimization techniques comes with its own benefits and overheads while there are also too many of them. Thus, here comes the problem of when and how such optimization techniques should be applied. In order to solve this problem, we build a runtime framework to throttle these optimization techniques based on concise performance and energy models. With the help of this framework, we can successfully establish adaptive selections over multiple optimization techniques to further improve performance or energy efficiency of the network at runtime.

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The SiLago Solution: Architecture and Design Methods for a Heterogeneous Dark Silicon Aware Coarse Grain Reconfigurable Fabric

Hemani

Farahini

Jafri

et al. 2017

The Dark Side of Silicon

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Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs

Abstract: This paper proposes an ultra fine-grained run-time power gating of on-chip router, in which power supply to each router component (e.g., VC queue, crossbar MUX, and output latch)

Cited by 62 publications

References 18 publications

Network on Chip Router with Power Management Unit for Improved Network Fabric Power Efficiency

Network on Chip Router with Power Management Unit for Improved Network Fabric Power Efficiency

A Runtime Optimization Selection Framework to Realize Energy Efficient Networks-on-Chip

The SiLago Solution: Architecture and Design Methods for a Heterogeneous Dark Silicon Aware Coarse Grain Reconfigurable Fabric

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