The SiLago Solution: Architecture and Design Methods for a Heterogeneous Dark Silicon Aware Coarse Grain Reconfigurable Fabric

Hemani, Ahmed; Farahini, Nasim; Jafri, Syed M. A. H.; Sohofi, Hassan; Li, Shuo; Paul, Kolin

doi:10.1007/978-3-319-31596-6_3

Cited by 9 publications

(4 citation statements)

References 36 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In many of today's designs, many circuit paths will be "dark" at any given moment. Hence, the power consumption rate will consider power to only a fraction of a chip which results the percentage of the chip which is active with generation of each processor to be exponentially smaller [2].…”

Section: A Dark Silicon Constraintmentioning

confidence: 99%

“…As we know that the dark silicon constraint prevents transistors more than a pre-defined number to turn on at a time, we need to use transistors with high silicon and computational efficiency.To tackle this, VLSI experts have suggested two solutions: Heterogeneity of processors and use of accelerators. Also, if we want to tackle the cost due to steep engineering, we have to settle on designs which are platform-based and con-sists of mostly general-purpose processors and interconnects associated to them [2].…”

Section: A Dark Silicon Constraintmentioning

confidence: 99%

See 1 more Smart Citation

From DNNs to GANs: Review of efficient hardware architectures for deep learning

Bhattacharya¹

2021

Preprint

View full text Add to dashboard Cite

In recent times, the trend in very large scale integration (VLSI) industry is multi-dimensional, e.g. reduction of energy consumption, occupancy of less space, precise result, less power dissipation, faster response etc. To meet these needs, the hardware architecture should be reliable and robust to these problems. Recently, neural network and deep learning has been started to impact the present research paradigm significantly which consists of parameters in the order of millions, nonlinear function for activation, convolutional operation for feature extraction, softmax regression for classification, generative adversarial networks, etc. These operations involve huge calculation and memory overhead. Presently available DSP processors are incapable of performing these operations and they most face the problems e.g. memory overhead, performance drop and compromised accuracy. Moreover, if a huge silicon area is powered to accelerate the operation using parallel computation, the IC's will be having significant chance of burning out due to the considerable generation of heat. Hence, novel dark silicon constraint is developed to reduce the heat dissipation without sacrificing the accuracy. Similarly, different algorithms have been adapted to design a DSP processor compatible for fast performance in neural network, activation function, convolutional neural network and generative adversarial network. In this review, we illustrate the recent developments in hardware for accelerating the efficient implementation of deep learning networks with enhanced performance. The techniques investigated in this review are expected to direct future research challenges of hardware optimization for high-performance computations.

show abstract

Section: A Dark Silicon Constraintmentioning

confidence: 99%

Section: A Dark Silicon Constraintmentioning

confidence: 99%

From DNNs to GANs: Review of efficient hardware architectures for deep learning

Bhattacharya¹

2021

Preprint

View full text Add to dashboard Cite

show abstract

“…SiLago (Silicon Large Grain Objects) [103] is a methodology for creating CGRA-based platforms. The premise behind the method is to use reconfigurable CGRA processing elements (based on DRRA [104]) as building blocks for future systems in order to reduce production cost with little impact on performance (compared to hand-made ASICs).…”

Section: B Modern Coarse-grained Reconfigurable Architecturesmentioning

confidence: 99%

A Survey on Coarse-Grained Reconfigurable Architectures From a Performance Perspective

2020

View full text Add to dashboard Cite

show abstract

“…To show the flexibility of the method to support different applications and hardware platforms, we applied our methods to two hardware architectures with varying constraints. The first is SiLago architecture [22], and the second is Bitfusion architecture [23]. These two architectures are chosen as they support the varying precision required in our experiments.…”

Section: Introductionmentioning

confidence: 99%