UltiMOS: A local charge-balanced trench-based 600V super-junction device

“…Another alternative is the deposition of two epitaxial layers (n and p-type) on the vertical walls of deep trenches, which was first reported by Infineon [12], showing a theoretical 50% reduction of R ON-SP in comparison with a 600V CoolMOS. Recently, ON Semiconductor has also reported the UltiMOS structure [13], which is a local charge balanced trench super-junction MOSFET characterized by the selectively growth of both n-type and p-type thin layers on the vertical walls of a deep trench structure. Figure 2 shows a microphotograph of a 730V device with an R ON-SP of 23 mΩcm…”

Section: 5mentioning

confidence: 99%

“…An optimization of this structure in terms of the vertical electric field distribution requires an asymmetric structure, which is characterized by an oxide thickness increase in Fig. 2: Microphotograph of the UltiMOS structure [13] the vertical direction (GOB, Gradient Oxide-Bypass) [17].…”

Section: 5mentioning

confidence: 99%

A Review of Si MOS-gated Power Switches and PiN Rectifiers

et al. 2012

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Original scientific paperRevolutionary advances and developments have been made in power semiconductor device technologies during the last decades which have allowed the improvement of power electronic systems in terms of their efficiency and reliability. The advent of MOS-gated power switches such as the power MOSFET and the IGBT showing high input impedance has been a real breakthrough in the design and fabrication of power electronic systems. This paper reviews the recent progress in the development of Si MOS-gated power devices and rectifiers. The evolution of these devices' technologies together with the introduction of revolutionary device concepts is also discussed. Concretely, the introduction of trench technologies for power MOSFETs and the use of the super-junction concept for breaking the 1D-silicon limit are highlighted. Developments in IGBTs such as those based on the use of thin wafers and strategies for optimising the plasma distribution in PT IGBTs during the on-state are also addressed. Finally, advances in PiN diode technologies including new concepts for both the anode and the cathode structures are also reviewed. These approaches have allowed the reduction of the PiN total losses and a soft reverse recovery behaviour, leading to a more rugged device.Key words: MOS-gated power devices, power MOSFETs, CoolMOS, super-junction devices, IGBTs, PiN rectifiers Prikaz stanja silicijevih MOS upravljanih učinskih sklopova i PiN ispravljača. U posljednjim desetljećima svjedočimo razvoju sustava učinske elektronike u pogledu povećanja efikasnosti i pouzdanosti. Napredak je omogućen zahvaljujući izvanrednom napredku koji je postignut na području učinskih poluvodiča. Pojava MOS upravljanih učinskih sklopova s visokom ulaznom impedancijom, kao što su MOSFET i IGBT, rezultirao je probojem u projektiranju i proizvodnji sustava učinske elekronike. Ovajčlanak daje uvid u napredak koji je u posljednje vrijeme ostvaren u razvoju silicijeve MOS upravljane učinske elektronike i ispravljača. Uz dosadašnji razvoj tehnologije navedenih komponenata, učlanku je uključen i osvrt na revolucionarne koncepte budućeg razvoja. Konkretno, u radu su objašnjene tehnologija rova za MOSFET i korištenje koncepta super spoja za probijanje granice jednodimenzionalnog silicija. Razmatrana su i poboljšanja IGBT-ova koja se baziraju na uporabi tankih pločica a strategijama optimiranja distribucije plazme u PT IGBT-ovima za vrijeme aktivnog stanja. Konačno, prikazan je i napredak u tehnologiji PiN dioda koji uključuje nove strukturalne koncepte katode i anode. Ovi pristupi su omogućili smanjenje ukupnih gubitaka PiN diode i blagu dinamiku reverznog oporavka, što rezultira povećanjem robusnosti sklopa.

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“…The P body is connected to the anode electrode and the N link is placed in between the P body and N À epi regions. In the SJ MOSFET [8] the P body is used to create the n-channel and the N link is used to connect the end of the channel (bottom of the gate trench) to the conducting N-type drift layer (top of the N pillar ).…”

Section: Device Structure Descriptionmentioning

confidence: 99%

“…In order to avoid the potential effect of the MOSFET parasitic bipolar on the device reliability, 600 V-10A rated SJ diodes are analyzed. These diodes are fabricated according to the generic UltiMOS [8] process flow, with the exception of the N + implant and the gate trench. The device is based on the local CB between two thin highly doped pillars grown on the sidewall of deep trenches.…”

Section: Introductionmentioning

confidence: 99%