Two-Step Write Scheme for Reducing Sneak-Path Leakage in Complementary Memristor Array

Jung, Chul-Moon; Choi, Jun-Myung; Min, Kyeong‐Sik

doi:10.1109/tnano.2012.2188302

Cited by 66 publications

(44 citation statements)

References 26 publications

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“…To do so, we considered the non-linear dopant kinetics which are dominant at the boundaries of resistive switching in the Verilog-A model [20,21]. Before we developed the memristor Verilog-A model, we should consider memristive behavior first.…”

Section: Simulation Resultsmentioning

confidence: 99%

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Dynamic Reference Scheme with Improved Read Voltage Margin for Compensating Cell-position and Background-pattern Dependencies in Pure Memristor Array

Shin¹,

Byeon²,

Song³

et al. 2015

JSTS:Journal of Semiconductor Technology and Science

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Abstract-In this paper, a new dynamic reference scheme is proposed to improve the read voltage margin better than the previous static reference scheme. The proposed dynamic reference scheme can be helpful in compensating not only the background pattern dependence but also the cell position dependence. The proposed dynamic reference is verified by simulating the CMOS-memristor hybrid circuit using the practical CMOS SPICE and memristor Verilog-A models. In the simulation, the percentage read voltage margin is compared between the previous static reference scheme and the new dynamic reference scheme. Assuming that the critical percentage of read voltage margin is 5%, the memristor array size with the dynamic scheme can be larger by 60%, compared to the array size with the static one. In addition, for the array size of 64 x 64, the interconnect resistance in the array with the dynamic scheme can be increased by 30% than the static reference one. For the array size of 128 x 128, the interconnect resistance with the proposed scheme can be improved by 38% than the previous static one, allowing more margin on the variation of interconnect resistance.Index Terms-Dynamic reference scheme, read voltage margin, cell-position and background-pattern dependencies, pure memristor array

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Section: Simulation Resultsmentioning

confidence: 99%

“…The threshold behaviors and window function are also included in the circuit simulation for verifying the proposed dynamic reference scheme [20,21]. Fig.…”

Section: Simulation Resultsmentioning

confidence: 99%

Dynamic Reference Scheme with Improved Read Voltage Margin for Compensating Cell-position and Background-pattern Dependencies in Pure Memristor Array

Shin¹,

Byeon²,

Song³

et al. 2015

JSTS:Journal of Semiconductor Technology and Science

Self Cite

View full text Add to dashboard Cite

show abstract

“…To overcome the sneak path problem, application of access transistors and diodes have been proposed in literature [32] that facilitate selective and disturb-free write operations. Methods for programming memristors without access transistors have also been suggested, but using such techniques, only a single device in an array can be programmed at a time [30,31]. Such schemes can be applicable only if programming speed is not a major concern.…”

Section: Htm Design Specificationmentioning

confidence: 99%

Hierarchical Temporal Memory Based on Spin-Neurons and Resistive Memory for Energy-Efficient Brain-Inspired Computing

Fan

Sharad

Sengupta

et al. 2016

IEEE Trans. Neural Netw. Learning Syst.

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“…R o f f ", as introduced in [47]. Having always a high resistance cell reduces the sneak-path current significantly.…”

Section: Complimentary Memristorsmentioning

confidence: 99%

Memristor-based memory: The sneak paths problem and solutions

Zidan

Fahmy

Hussain

et al. 2013

Microelectronics Journal

377

195

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In this paper, we investigate the read operation of memristor-based memories. We analyze the sneak paths problem and provide a noise margin metric to compare the various solutions proposed in the literature. We also analyze the power consumption associated with these solutions. Moreover, we study the effect of the aspect ratio of the memory array on the sneak paths. Finally, we introduce a new technique for solving the sneak paths problem by gating the memory cell using a three-terminal memistor device.

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Two-Step Write Scheme for Reducing Sneak-Path Leakage in Complementary Memristor Array

Cited by 66 publications

References 26 publications

Dynamic Reference Scheme with Improved Read Voltage Margin for Compensating Cell-position and Background-pattern Dependencies in Pure Memristor Array

Dynamic Reference Scheme with Improved Read Voltage Margin for Compensating Cell-position and Background-pattern Dependencies in Pure Memristor Array

Hierarchical Temporal Memory Based on Spin-Neurons and Resistive Memory for Energy-Efficient Brain-Inspired Computing

Memristor-based memory: The sneak paths problem and solutions

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