Two-step Electrical Degradation Behavior in α-InGaZnO Thin-film Transistor Under Gate-bias Stress

Chen, Fa-Hsyang; Pan, Tung-Ming; Chen, Ching-Hung; Liu, Jiang-Hung; Lin, Wen-Wei; Chen, Po-Hsueh

doi:10.1109/led.2013.2248115

Cited by 39 publications

(23 citation statements)

References 12 publications

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“…We suspect that these species are located in the SiO 2 etch-stopper layer in accordance with Ref. 17, but we do not exclude the likelihood of the semiconductor or gate dielectric layer being contaminated.…”

Section: -5mentioning

confidence: 66%

“…16 In Ref. 17, the authors propose that the SiO 2 etch-stopper layer embedded with H 2 O molecules may cause negative V TH shift under PBS, releasing extra electrons to IGZO. So we propose that equations (7) and (8) may be interpreted as electron-donating reaction rate involving H 2 O molecules or derived OH species that are present in the TFT from fabrication process or from interaction with ambient air during storage.…”

Section: -5mentioning

confidence: 99%

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Interpreting anomalies observed in oxide semiconductor TFTs under negative and positive bias stress

et al. 2016

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Oxide semiconductor thin-film transistors can show anomalous behavior under bias stress. Two types of anomalies are discussed in this paper. The first is the shift in threshold voltage (VTH) in a direction opposite to the applied bias stress, and highly dependent on gate dielectric material. We attribute this to charge trapping/detrapping and charge migration within the gate dielectric. We emphasize the fundamental difference between trapping/detrapping events occurring at the semiconductor/dielectric interface and those occurring at gate/dielectric interface, and show that charge migration is essential to explain the first anomaly. We model charge migration in terms of the non-instantaneous polarization density. The second type of anomaly is negative VTH shift under high positive bias stress, with logarithmic evolution in time. This can be argued as electron-donating reactions involving H2O molecules or derived species, with a reaction rate exponentially accelerated by positive gate bias and exponentially decreased by the number of reactions already occurred.

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Section: -5mentioning

confidence: 66%

Section: -5mentioning

confidence: 99%

Interpreting anomalies observed in oxide semiconductor TFTs under negative and positive bias stress

et al. 2016

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“…They often exhibits depletion-mode characteristics due to narrow process window and by external influences such as illumination and bias stress [3,4,5]. As a result, a considerable amount of current may flow at zero gate-to-source bias (V GS ).…”

Section: Introductionmentioning

confidence: 99%

5 V input level shifter circuit for IGZO thin-film transistors

Lym

et al. 2014

IEICE Electron. Express

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A 5 V input level shifter circuit based on depletion-mode In-Ga-Zn-O thin-film transistors (TFT) worked up to 100 kHz. By employing metal-insulator-semiconductor (MIS) active capacitor, we enhanced the bootstrapping effect and reduced the rise time of the output signal. SPICE simulation results showed that the proposed level shifter worked for wide threshold voltage range from !2 V to D1 V and the fabricated circuit exhibited the propagation delay t plh and t phl of 0.6 µsec and 0.3 µsec respectively.

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“…They exhibit superior performance to the amorphous silicon (a-Si) TFTs and lower process cost than the lowtemperature polycrystalline silicon (LTPS) TFTs [1,2]. However, they often have negative threshold voltage (V T ) by process fluctuation and biasillumination stress [3,4,5]. Therefore the display-driving circuit such as shift register does not work or exhibit anomalously large power consumption when we adopt conventional circuit structures.…”

Section: Introductionmentioning

confidence: 99%

A shift register for depletion-mode oxide TFTs with very low power consumption

Park

Kim

Jang

et al. 2013

IEICE Electron. Express

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Abstract:The shift register comprised of metal-oxide thin-film transistors (TFTs) is apt to exhibit anomalously high power consumption because the oxide TFT often has depletion-mode characteristic. We have developed a new shift register circuit in which one of the pull-down TFTs is controlled by capacitive coupling with the clock signal and the input carry signal. Employing this structure, the TFTs with non-zero V DS are always turned off with negative V GS . As a result, unnecessary current through the TFTs is eliminated and the power consumption of the new circuit decreases to the half of our previous one when the threshold voltage of the TFT is À5 V.

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Two-step Electrical Degradation Behavior in α-InGaZnO Thin-film Transistor Under Gate-bias Stress

Cited by 39 publications

References 12 publications

Interpreting anomalies observed in oxide semiconductor TFTs under negative and positive bias stress

Interpreting anomalies observed in oxide semiconductor TFTs under negative and positive bias stress

5 V input level shifter circuit for IGZO thin-film transistors

A shift register for depletion-mode oxide TFTs with very low power consumption

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