Two-resistor compact modeling for multiple die and multi-chip packages

Garcia, EA; Chiu, Charles B.

doi:10.1109/stherm.2005.1412200

Cited by 13 publications

(9 citation statements)

References 3 publications

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“…The physical attributes of tested stacked chip scale package (SCSP) can be found in [7]. Only a half of the cavity was included in the model for the simulation to save the computation time, however, this simplification is expected to have minimal effect on overall flow pattern, due to thinner cavity z-height compared to the span-wise spacing between packages in the panel.…”

Section: Resultsmentioning

confidence: 99%

Three Dimensional Flow Analysis During Injection Molding Process For Stacked-Die Packages

Moon

Cheng

et al. 2007

2007 32nd IEEE/CPMT International Electronic Manufacturing Technology Symposium

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The three-dimensional numerical simulation has been performed to study mold flow characteristics during injection molding process of stacked die packages. The modeling results revealed that flow front shape is highly non-uniform around the die stack-up units and is dependent on various design parameters including mold cap clearance, mold compound material properties, as well as the die stack-up geometric configurations. It was demonstrated that validated flow model can help guiding the design, material, and process optimization of 3D packaging development. IntroductionAs the demand for speed and functionality increases for electronic handheld devices such as cell phones and PDAs, a stacked die package becomes one of the preferred options to provide the high performance and multi-functionality for a given electronic component. While the injection molding process is widely used for the microchip encapsulation, the various design, materials and process parameters will need to be further optimized for defect free process due to the increased level of complexity in package architecture.There have been studies of mold filling analysis in microchip encapsulation, however, focuses were given to the single die, not to 3D packaging such as staked-die packages [1][2][3][4]. Therefore, in this study, a three dimensional computational fluid dynamics (CFD) analysis has been performed on a stacked-die package, using a commercially available injection-molding software package, Moldflow, to establish the understanding of the mold flow characteristics in the complicated geometry during the encapsulation process on the effect of different design parameters. Numerical Model DescriptionThe mass, momentum, and energy conservations for mold flow in the filling phase can be mathematically described by equations (1) through (3), respectively [2,5].-P+V(pv)0=0 (1) at (, +V(pvv)=-Vp+Vr+pg (2) OT (,cupat VT ,8'at i+y'+kVT+H at where iv is the velocity vector, p the density, 77 the viscosity, p the static pressure, r the stress tensor, and y the shear rate. Also the first term in the right hand side in equation (3) is the energy generation rate due to compression/expansion of the polymer melt followed by the energy generation rate due to viscous dissipation. The last term in equation (3) is the exothermic heat generation rate due to curing, where a is the degree of cure and H is the total heat of the cross linking reaction.In this simulation, the curing reaction is described with Kamal's autocatalytic model as shown in equation (4). (4) 3r= (K1 +K2ajXI-a)' K is the Arrhenius equation constant; m and n are the reaction orders. The temperature Arrhenius equation constant K is commonly described by equation (5).Ki Ai exp RT (5) Ai is the pre-exponential factor; Ei is the activation energy; R is the universal gas constant.For the non-Newtonian viscosity behavior of the polymer melt, the Cross-Exponential Macosko model [6] is used as described by following equation.

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Section: Resultsmentioning

confidence: 99%

Three Dimensional Flow Analysis During Injection Molding Process For Stacked-Die Packages

Moon

Cheng

et al. 2007

2007 32nd IEEE/CPMT International Electronic Manufacturing Technology Symposium

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“…The paper of the same authors discusses further the accuracy of these very simple 1 or 2 resistor compact models [9]. The merit of their experiments is that several stacked die structures were packaged in various types of packages, and a number of measurements support the conclusions of the paper.…”

Section: Steady State Compact Modeling Of Stacked Diementioning

confidence: 89%

“…While single die package compact thermal modeling has a broad literature, the questions of compact modeling of stacked die packages has been discussed much less so far, some introductory discussions are presented in [7][8][9][10]. Standardized metrics, as proper extension of the single die R th concept are also needed for multiple dice packages.…”

Section: Figure 1: Typical Realization Of Stacked Die Packagesmentioning

confidence: 99%

Thermal qualification of 3D stacked die structures

Rencz

2006

2006 International Biennial Baltic Electronics Conference

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After an introductory discussion of the thermal issues in stacked die packages in general, two major subjects are discussed in the paper: the qualification of die attach in stacked die structures and the questions of compact thermal modeling. An overview is given about the currently used techniques for the qualification of the die attach for failure analysis in stacked structures. The third part of the paper presents the state-of-theart and the major issues of compact thermal modeling of stacked die packages. A methodology is suggested for the transient compact modeling of stacked die structures.

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“…A typical detailed thermal model for a stacked chip scale package (SCSP) is illustrated together with its BGA in Figure 2. This model was constructed under the θ ja and θ jb environments as per JEDEC JESD51-2 [2] and JESD51-8 [3] guides, respectively. Then empirical data was collected and used to validate detailed component-level thermal model.…”

Section: Validated Package Detailed Modelmentioning

confidence: 99%

“…Figure 5 presents the sensitivity study results of TDP ratio with an increase of thermal conductivity of die attach under different thermal boundary conditions -θ ja , θ jb , and θ jc . Detailed description of θ jc metrologies for modeling and measurement can be found in [4] and [5], respectively. Baseline materials were used for other packaging materials.…”

Section: Thermally Conductive Packaging Materialsmentioning

confidence: 99%

Optimization of packaging materials and design for thermal management in stacked-die packages

Moon

Dizon²,

Chiu³

et al.

Thermal and Thermomechanical Proceedings 10th Intersociety Conference on Phenomena in Electronics Systems, 2006. ITHERM 2006.

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Various package level thermal management schemes are discussed. Extensive sensitivity study data of thermally conductive packaging materials such as die adhesive, mold compound, and board level underfill are reviewed on different package architectures by using JEDEC standards. Thermal benefits of heat spreader embedded stacked-die packages are also investigated. By using the validated detailed package thermal model, the design cycle and time-to-market can be significantly reduced.

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Two-resistor compact modeling for multiple die and multi-chip packages

Cited by 13 publications

References 3 publications

Three Dimensional Flow Analysis During Injection Molding Process For Stacked-Die Packages

Three Dimensional Flow Analysis During Injection Molding Process For Stacked-Die Packages

Thermal qualification of 3D stacked die structures

Optimization of packaging materials and design for thermal management in stacked-die packages

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