2019 IEEE Applied Power Electronics Conference and Exposition (APEC) 2019
DOI: 10.1109/apec.2019.8722007
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Two-Level Algorithm for UPQC Considering Power Electronic Converters and Transformers

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Cited by 9 publications
(5 citation statements)
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“…In order to achieve the minimum UPAC load in this design, in addition to controlling the injection voltage by series transformers, the parallel inverter current is also included in the power optimization process [93].…”
Section: K Voltage Dip Compensation Based On Minimum Apparent Power (...mentioning
confidence: 99%
“…In order to achieve the minimum UPAC load in this design, in addition to controlling the injection voltage by series transformers, the parallel inverter current is also included in the power optimization process [93].…”
Section: K Voltage Dip Compensation Based On Minimum Apparent Power (...mentioning
confidence: 99%
“…In [133], a two-stage optimization control algorithm based on the variable PAC method is proposed for the optimal design of UPQC. In a two-level algorithm, both the transformer VA rating and capital cost are considered for optimization [134]. In [135], a superconducting fault current limiter (SFCL) is connected to the parallel feeder of the main feeder where the UPQC is connected.…”
Section: Optimum Upqc Design Based On Kva Ratingmentioning
confidence: 99%
“…The power quality improvement in smart grid environment is implemented in [1] using modified UPQC topology. A new algorithm for UPQC is proposed in [2]. A single-stage quasi UPQC is implemented in [3].…”
Section: Introductionmentioning
confidence: 99%