Twelve-bit 20-GHz reduced size pipeline accumulator in 0.25 [micro sign]m SiGe:C technology for direct digital synthesiser applications

Jensen, Brian Sveistrup; Khafaji, Mohammad Mahdi; Johansen, Tom K.; Krozer, Viktor; Scheytt, J. Christoph

doi:10.1049/iet-cds.2010.0399

Cited by 13 publications

(8 citation statements)

References 17 publications

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“…As an example, in [2][3][4], this technique is applied to produce 9-, 12-, and 8-bit pipelined PA respectively. Another pipelined technique without pre-skewing registers in the pipelining levels is used in [5] to construct 12-bit PA. In addition to the XOR gates, a different types of speed registers are to complement the most-significant bits (MSB) values.…”

Section: Pipelinied Phase Accumulator Designmentioning

confidence: 99%

Review of high-speed phase accumulator for direct digital frequency synthesizer

Abbas¹

2020

IJECE

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A review of high-speed pipelined phase accumulator (PA) is proposed in this paper. The detail explanation of ideas, methods and techniques used in previous researches to improve the PA throughput designs were surveyed. The Brent–Kung (BK) adder was modified in this paper to be applied in pipelined PA architecture. A comparison of different adder circuits, includes a modified BK, ripple carry adder (RCA), Kogge-Stone adder (KS) and other prefix adders were applied to architect the PA based on Pipeline technique. The presented pipelined PA design circuit with multiple frequency control word (FCW) and different adders were coded Verilog hardware description language (HDL) code, compiled and verified with field programmable gate array (FPGA) kit platform. The comparison result shows that the modified BK adder has fast performances. The shifted clocking technique is utilized in the proposed pipelined PA circuit to reduce the unwanted repetitive D-flip flop (DFF) registers (coming from the pipeline technique), while preserving the high speed.

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Section: Pipelinied Phase Accumulator Designmentioning

confidence: 99%

Review of high-speed phase accumulator for direct digital frequency synthesizer

Abbas¹

2020

IJECE

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“…Hence, the PA, which would consist of D flip flop (DFF) registers and adders, taking in consideration the use of fast adders as well as applying the pipelining techniques as in [2,3], will provide the desired requirements. Several solutions have proposed the pipelining design technique to improve speed performance and reduce complexity for the PA [4]. However, this technique has the disadvantage of increasing the number of registers as the pipeline stages increase.…”

Section: Introductionmentioning

confidence: 99%

A low power memoryless ROM design architecture for a direct digital frequency synthesizer

Alkurwy

Ali²,

Islam

et al. 2017

Turk J Elec Eng & Comp Sci

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This paper presents a novel, memoryless, read-only memory (ROM) design architecture for a direct digital frequency synthesizer (DDFS). A pipelining technique is proposed to increase the phase accumulator (PA) throughput.However, this technique increases the number of registers as the pipeline stages increase. The shifted clocking technique is used to reduce the pipelined PA registers. The wave symmetry technique is applied to store (0: π /2) of the sine wave.The ROM is partitioned into three four-bit sub-ROMs based on the angular decomposition technique and trigonometric identity. A novel approach of memoryless ROM design technique is proposed and implemented in the design of a 24-bit DDFS system that replaces the conventional ROM. Replacing the memoryless sub-ROM circuits, instead of the conventional 12-bit ROM, reduces power consumption and area dimension. As a result, compared to the conventional ROM circuit, the values of area dimension and dynamic power are reduced by 15% and 14.8%, respectively.

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“…SiGe technology has higher thermal conductivity and better integration capability than InP. The accumulator size in SiGe can be more than 10-bits [8], thus capable of generating more than two thousands frequency points. The number of frequency points is important since fundamentally it allows user to tune finer output frequencies.…”

Section: Power Consumption Integration Capability Frequency Resolutionmentioning

confidence: 99%

“…First, the requirement of the numbers of the transistor would exceed several thousand and is a challenge for the new technology (SG13G2) adaption as the reliability is not well-understood for very-large integration of the transistors. The SG25H4 is highly stable and proven for the measured chip that consists of transistors count beyond 4 thousand [8]. A second reason, the SG13G2 would cost three times more than SG25H4.…”

Section: Technology Selection and Goalsmentioning

confidence: 99%

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SiGe based ROM-less 18.5 GHz clock direct digital synthesizer design and characterization

Shrestha¹

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The requirement of the versatile signal generator has always been evident in modern RF and communication systems. The most conventional technique, voltage control oscillator (VCO), has inferior phase noise and narrow bandwidth despite its operating frequency can be up to the sub-THz regime. Its phase noise influenced by a various parameter associated with the oscillator circuit e.g. transistor size \& noise, bias current, noise leaking from the bias supply etc. The bandwidth is limited because the input voltage \& the output frequency of the VCO is not strictly linear over the tuning range. The phase noise and SFDR of the VCO output are enhanced by using the phase-lock technique. The phase-locked loop (PLL) uses the feedback system locking the reference frequency set by the VCO. However, the settling time of the PLL is higher due to a feedback control loop. The higher settling time increases the frequency switching time between PLL outputs. IG-oscillators is suitable for multi-GHz range and wide bandwidth application. Signal generation can alos be achieved by the free-electron radiation, optical lasers, Gunn diodes as well and they can operate even at the THz domain. All these signal generators suffer from slow frequency switching, lack of digital controllability, and advance modulation capability even though their frequency of operation is THz regime. Alternatively, the AWG (arbitrary wave generator) can produce a wide range of frequencies with low phase noise, including digital controllability. One of the vital components of the AWG is the direct digital synthesiser (DDS). Generally, it is composed of a phase accumulator, digital to analogue converter, sine mapping circuits and low pass filter. It needs a reference clock that acts as samples of the DDS outputs. Its output frequency can be varied by applying an appropriate digital input code. But high-speed DDS has several limitations; such as low number of output frequency points, lack of phase control unit, high power consumptions etc. This work addresses such limitations.

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Twelve-bit 20-GHz reduced size pipeline accumulator in 0.25 [micro sign]m SiGe:C technology for direct digital synthesiser applications

Cited by 13 publications

References 17 publications

Review of high-speed phase accumulator for direct digital frequency synthesizer

Review of high-speed phase accumulator for direct digital frequency synthesizer

A low power memoryless ROM design architecture for a direct digital frequency synthesizer

SiGe based ROM-less 18.5 GHz clock direct digital synthesizer design and characterization

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