2019
DOI: 10.1038/s41928-019-0272-8
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Tunnelling-based ternary metal–oxide–semiconductor technology

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Cited by 88 publications
(48 citation statements)
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“…3a. This logical signal reversal by light modulation exhibits some similar features to optical inversion devices [40][41][42][43] . When the thickness of the intermediate transport layer exceeds or approaches the effective built-in electric field length, the entire system can be split into two parts, as displayed in Fig.…”
Section: Resultsmentioning
confidence: 81%
“…3a. This logical signal reversal by light modulation exhibits some similar features to optical inversion devices [40][41][42][43] . When the thickness of the intermediate transport layer exceeds or approaches the effective built-in electric field length, the entire system can be split into two parts, as displayed in Fig.…”
Section: Resultsmentioning
confidence: 81%
“…Particularly, neuromorphic systems on chips based on binary CMOS have been demonstrated by using parallelized neuro synaptic cores and spiking neural networks with low-frequency operations. Furthermore, for the significant increase of information density, the wafer-level integrated ternary CMOS (T-CMOS) using tunneling has been successfully reported and the possibility for the mass production of the T-CMOS neuromorphic system has been presented [27]. These ternary logics can reduce the number of transistors as compared to binary logics [28].…”
Section: Introductionmentioning
confidence: 99%
“…However, since the ternary state are implemented by the tunneling mechanism, the switching speed of the ternary inverters is relatively too slow compared to the conventional binary inverters. Nevertheless, the T-CMOS can operate a single comparator with two internal references in a 1.5 bit stage of a pipelined analogue-to-digital converter (ADC) [27]. As ADCs are necessary for integrated circuit designs, in the neuromorphic system which works at a low operating frequency (∼1kHz) [25], [26], it is expected that the ternary inverter can enhance the computation density as contrast to the binary inverter.…”
Section: Introductionmentioning
confidence: 99%
“…Specifically, the maximum noise margin of a ternary logic circuit is 33% of the VDD (VDD is divided by three logic states), while the maximum noise margin of a binary logic circuit is 50% of the VDD (VDD is divided by two logic states). 24 As a result, it is very important to accurately control each logic state margin circuit as the number of logic level states increases. However, previously reported vdW-H-based ternary circuits include: (1) incomplete output voltage swing [25][26][27] and (2) narrow margin for the intermediate-logic state.…”
Section: Introductionmentioning
confidence: 99%