Tunneling gate oxide approach to ultra-high current drive in small geometry MOSFETs

Momose, H.S.; Ono, Mizuki; Yoshitomi, T.; Ohguro, T.; Nakamura, Shigenari; Saito, M.; Iwai, Hiroshi

doi:10.1109/iedm.1994.383340

Cited by 86 publications

(53 citation statements)

References 2 publications

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“…[3]. could still be used as gate dielectric [14,15]. In the early 1990s, 100-nm was thought to be the limit because of many expected difficulties in reducing the physical parameters of the transistors.…”

Section: Introduction and Overviewmentioning

confidence: 99%

On the scaling issues and high-κ replacement of ultrathin gate dielectrics for nanoscale MOS transistors

Wong

Iwai

2006

Microelectronic Engineering

350

184

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Section: Introduction and Overviewmentioning

confidence: 99%

On the scaling issues and high-κ replacement of ultrathin gate dielectrics for nanoscale MOS transistors

Wong

Iwai

2006

Microelectronic Engineering

350

184

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“…The component of gate leakage current can to be ignored in MOSFETs with smaller gate length, because of the shrinkage in the gate area which leads to the decrease in leakage current, associated with the increase in drain current (6). The gate leakage component can be subtracted from the drain current with the use of currents monitored at source and gate (7).…”

Section: Resultsmentioning

confidence: 99%

Overwhelming the 0.5 nm EOT Level for CMOS Gate Dielectric

Kakushima

Ahmet

2009

ECS Trans.

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MOSFET with EOT below 0.37 nm has been achieved with La 2 O 3 gate dielectric by realizing direct contact on Si. A sufficient increase in drain current has been observed while scaling the EOT from 0.48 to 0.37 nm. Therefore, continuous scaling of EOT below 0.5 nm is still effective for further improvement in device performance. Moreover, the EOT increment by La-silicate formation after high temperature annealing can be well suppressed under control of oxygen by selecting a metal gate.

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“…15 The direct-tunneling gate leakage current of the small channel gate area was still sufficiently negligible so as not to affect the I d -V d characteristics. Thus, SiO 2 film with a small concentration of nitrogen 16 with thickness less than 3 nm has been used for LSIs since then.…”

Section: 12mentioning

confidence: 92%

High Dielectric Constant Materials for Nanoscale Devices and Beyond

Toriumi

Misra

2017

Electrochem. Soc. Interface

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Tremendous progress of CMOS integrated circuits have been conducted by the down-scaling or the miniaturization of MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). Ten years, ago, the huge direct-tunneling gate leakage current through the thin gate SiO2 film of 1 nm thickness made it impossible to further scale-down the MOSFETs, and replacing the SiO2 by HfO2-based higher-dielectric constant (high-k) material was the solution. In this paper, the history of high-k gate insulator film development and two topics from recent research results regarding ferroelectricity and reliability are described.

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Tunneling gate oxide approach to ultra-high current drive in small geometry MOSFETs

Cited by 86 publications

References 2 publications

On the scaling issues and high-κ replacement of ultrathin gate dielectrics for nanoscale MOS transistors

On the scaling issues and high-κ replacement of ultrathin gate dielectrics for nanoscale MOS transistors

Overwhelming the 0.5 nm EOT Level for CMOS Gate Dielectric

High Dielectric Constant Materials for Nanoscale Devices and Beyond

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