Tuning of SnS Thin Film Conductivity on Annealing in an Open Air Environment for Transistor Application

Abstract

The study aimed at enhancement and optimisation of SnS conductivity via annealing for field effect transistor’s semiconductor channel layer application. Interstitials and vacancies in SnS films are known to cause carrier traps which limit charge carriers and hence limit the achievement of the threshold voltage for a field effect transistor operation. Tuning of SnS conductivity for transistor application is of emerging interest for novel device operation. SnS thin film semiconductors of 0.4 thickness were deposited using Aerosol assisted chemical vapour deposition and annealed in open air at annealing temperatures of150, 200, 250, 300 and 350 . Variation of the annealing temperature from 150 through 250 enhances the crystallinity of the annealed thin film samples by increasing the number of crystallites of the annealed films which is also buttress by the decreasing values of FWHM. However a further decrease in crystallite size at higher annealing temperature of 300 to 350 was observed which could be attributed to the fragmentation of clusters of crystallites at higher annealing temperature. Increase in annealing temperature increases grain size leading to the reduction in grain boundaries and potential barrier thereby changing the structure and phase of the films which in essence affects the electrical conductivity of the SnS thin films. The films annealed at 250 exhibited optimum conductivity. The average hall coefficients of the samples deposited at 150 to 250 were positive which indicates that the films annealed at this temperature range are of p type conduction while the average hall coefficients of the samples deposited at 300 and 350 were negative indicating that the films are of n type conduction. The conductivity change is essential for the use of SnS as a semiconductor channel layer especially in a field effect transistor where the device can be tuned to work as a p type or n type semiconductor channel layer.

Characteristics and Optical Properties of Bi2Te2.45Se0.55 Thin Film

“…These results confirm the structural investigations by X-ray, which indicates the increase of crystallinity of the films by annealing. This agrees well with the results of other works for chalcogenide materials [18]. The temperature dependence of electrical conductivity was investigated using Arrhenius equation [19]: EEJP.…”

“…The conductivity at room temperature for the as-deposited sample and annealed temperature 373, 473K are 3.6 x10 3 , 3.7 x10 3 , and 4.1x10 3 ohm -1 cm -1 respectively. This increase in conductivity by annealing may be attributed to the improvement of crystallite size and a decrease of defects' number which allows more carriers to flow through the system to take part in conduction [18]. These results confirm the structural investigations by X-ray, which indicates the increase of crystallinity of the films by annealing.…”

Optimization of electrical conductivity of SnS thin film of 0.2 < t ≤ 0.4 μm thicknes for field effect transistor application

“…From the table, the average Hall coefficient of all the deposited SnS thin films was found to be positive, which means that all the films possess conductivity of the p-type carrier. A similar form of thin film conductivity was reported by [18][19][20] among others for thin films of SnS. Several researchers have reported variations in the electrical resistivity of deposited SnS thin films to depend on lattice defects (e.g.…”

Liquid deposition modelling 3D printing of semiconductor tin sulphide (SnS) thin film for application in optoelectronic and electronic devices

“…The regulation of thin film thickness is crucial in SnS thin film semiconductor processing [4]. Due to the large number of small grains with large quantities of grain boundaries acting as an electron trap, pinholes, voids in a separate island-like state, and traps associated with certain film thickness affect charge carriers, affecting the electrical conductivity/properties, optical energy band gap, and threshold voltage for use in optoelectronics and electronics devices.…”