Tuning Caches to Applications for Low-Energy Embedded Systems

Abstract

Abstract:The power consumed by the memory hierarchy of a microprocessor can contribute to as much as 50% of the total microprocessor system power, and is thus a good candidate for power and energy optimizations. We discuss four methods for tuning a microprocessors' cache subsystem to the needs of any executing application for low-energy embedded systems. We introduce onchip hardware implementing an efficient cache tuning heuristic that can automatically, transparently, and dynamically tune a configurable level-one cache's total size, associativity and line size to an executing application. We extend the single-level cache tuning heuristic for a two-level cache using a methodology applicable to both a simulation-based exploration environment and a hardware-based system prototyping environment. We show that a victim buffer can be very effective as a configurable parameter in a memory hierarchy. We reduce static energy dissipation of on-chip data cache by compressing the frequent values that widely exist in a data cache memory.

Switchable cache: utilising dark silicon for application specific cache optimisations

“…Due to the critical nature of power and performance of modern computer systems, finding the optimal (or near optimal) cache configuration has become an important issue in computer system design. The literature contains many works which highlight [5][6][7][9][10][11][12] application dependent behaviour of cache performance and energy consumption. In [10], Liang and Mitra proposed a method to predict instruction cache hits for various applications at design time.…”

“…Design time cache tuning methods such as [5,[9][10][11] try to find a single optimal cache configuration for a single application. Designing switchable caches (and re-configurable caches) require identifying a set of cache configurations to optimise a number of applications, especially when the number of applications using the switchable cache is higher than the number of switchable configurations.…”

“…Schneider et al [11] present a fast simulation technique to select performance‐optimal cache configurations for various applications at design time. Gordon‐Ross et al [5] discussed tuning caches to reduce energy consumption.…”

“…Cache memories are consistently used to bridge the performance gap between processor and memory, and to reduce energy consumption in memory access [5, 6]. A cache can take numerous shapes or configurations in terms of Block Size , Set Size and Associativity .…”

Automatic application-specific microarchitecture reconfiguration

“…This tool exploits profile data collected from executions of an application on the base instruction set to guide the inclusion or exclusion of candidate new instructions. [2] performs analytical (hierarchical) searching of parameters in their own dimensions, with some full parameter exploration to avoid local minimal, for tuning multi-level cache for low-energy embedded systems. [23] explores design options of instruction and data caches, branch predictor, and multiplier, by dividing the search space into piece-wise linear models and solving their results using integer linear programming.…”