Tungsten-dual polymetal technology for low resistive gate electrode

Kim, Yong Soo; Sung, Min-Gyu; Park, Sung-Ki

doi:10.1016/j.sse.2010.03.001

Cited by 4 publications

(3 citation statements)

References 13 publications

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“…Both Rs and chemical composition of W 2 N is more sensitive to the NH3 purge time, which is consistent with XRD results. Decreasing chemical contribution of the WN x means that the inserted amorphous WN x diffusion barrier transforms to the crystallized W 2 N under the NH 3 pre-purge step of capping nitride deposition [5]. Comparison between chemical contribution (from XPS) and sheet resistance of W films under various NH 3 pre-purge time /temperature.…”

Section: Fig3 Thermal Stress Comparison Under Various Thermal Condimentioning

confidence: 99%

Stress induced self aligned contact failure during tungsten-poly gate process in sub-60 nm memory device

Sung¹,

Kim²,

Park³

2011

18th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)

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We investigated the mechanism of stress-induced self-aligned contact (SAC) failure in the sub-60 nm W-dual poly metal gate process in DRAM devices. It was found that during NH 3 pre-purge step of gate capping nitride deposition, amorphous WN x barrier and side of gate etched W electrode were transformed into tensile crystallized W 2 N, which relieves high compressive stress of inner gate W. Asymmetrical relief of W stress could create torque leading to gate leaning which is a main culprit of SAC failure during reliability test. Therefore, by reducing NH 3 pre-purge time, we successfully could reduce gate leaning which endures good reliability characteristics

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Section: Fig3 Thermal Stress Comparison Under Various Thermal Condimentioning

confidence: 99%

Stress induced self aligned contact failure during tungsten-poly gate process in sub-60 nm memory device

Sung¹,

Kim²,

Park³

2011

18th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)

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“…7 8 Some efforts involved using tungsten deposited by a chemical vapor deposition (CVD) method with a B 2 H 6 -based nucleation layer as an amorphous sub-layer. 7 Although this approach reduce the * Author to whom correspondence should be addressed. R s by increasing the W grain size, due to an amorphous nucleation layer which is independent of the crystallinity of the sub-layer, the high surface roughness of CVD W could lead to potential process issues such as over/under etch of Si at the source and drain during the gate etch process.…”

Section: Introductionmentioning

confidence: 99%

Optimization of Tungsten Dual Poly-Metal Gates in Memory Devices with Ti/WN/WSiN Barrier Metal

Sung¹,

Park²,

Ahmed³

et al. 2013

j. nanosci. nanotech.

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Due to the demand of high-speed/high-density and low power application of memory devices, tungsten dual poly gate (W-DPG; W/barrier metals/n+ and p+ poly-Si) electrode could be a good solution in order to reduce gate sheet resistance (Rs). Process optimization is completed for a diffusion barrier metal in a W-DPG. A new noble WSiN layer is inserted between the Ti/WN barrier metal and the tungsten gate electrode to maintain large grain size of W deposited by physical vapor deposition. The annealed WSiN during post-processing changes into crystallized WSi(x) mixed with SiN, which can make vertical conductive path between top and bottom interface, contributing to low vertical contact resistance (Rc) and low gate Rs adequate for high speed requirement of memory device. The Ti/WN/WSiN barrier is found to have the same electrical performance, ring oscillator singal delay as complicated multi-layes barrier metal, Ti/WN/TiN/WSi(x)/WN reported earlier. Therefore, the gate stack can be optimized by introducing a simpler diffusion barrier metal.

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“…[11][12][13][14] Other properties required for nanoscale patterning regarding factors such as contamination, morphology, resistance control, surface reaction, and patterning properties have been considered. 11,15 However, the oxidation of tungsten surfaces during processing is a critical problem that needs to be solved for the application of tungsten as the word line for nanoscale semiconductor devices.…”

Section: Introductionmentioning

confidence: 99%

Study on the oxidation and reduction of tungsten surface for sub-50 nm patterning process

Kim

Nam

Cho

et al. 2012

Journal of Vacuum Science &Amp; Technology A: Vacuum, Surfaces, and Films

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The oxidation characteristics of tungsten line pattern during the carbon-based mask-layer removal process using oxygen plasmas have been investigated for sub-50 nm patterning processes, in addition to the reduction characteristics of the WO x layer formed on the tungsten line surface using hydrogen plasmas. The surface oxidation of tungsten lines during the mask layer removal process could be minimized by using low-temperature (300 K) plasma processing for the removal of the carbon-based material. Using this technique, the thickness of WO x on the tungsten line could be decreased to 25% compared to results from high-temperature processing. The WO x layer could also be completely removed at a low temperature of 300 K using a hydrogen plasma by supplying bias power to the tungsten substrate to provide a activation energy for the reduction. When this oxidation and reduction technique was applied to actual 40-nm-CD device processing, the complete removal of WO x formed on the sidewall of tungsten line could be observed.

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Tungsten-dual polymetal technology for low resistive gate electrode

Cited by 4 publications

References 13 publications

Stress induced self aligned contact failure during tungsten-poly gate process in sub-60 nm memory device

Stress induced self aligned contact failure during tungsten-poly gate process in sub-60 nm memory device

Optimization of Tungsten Dual Poly-Metal Gates in Memory Devices with Ti/WN/WSiN Barrier Metal

Study on the oxidation and reduction of tungsten surface for sub-50 nm patterning process

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