TSV manufacturing yield and hidden costs for 3D IC integration

Lau, John H.

doi:10.1109/ectc.2010.5490828

Cited by 121 publications

(36 citation statements)

References 37 publications

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“…The yield of TSV bundle is only determined by the amount of TSV it includes because the TSV height variations of point-to-point link and bus are equal. Hence, the yield of chip can be obtained from the equation [5]. The enhancement in 3D chip yield brought by eliminating the number of TSV is conspicuous.…”

Section: Simulation Results and Performance Analysismentioning

confidence: 99%

“…An hybridization scheme for 3D NoC topology has been proposed in [4], which based on the stacked mesh and improved the architecture of bus. Vertical interconnect serialization technique [5] and the squeezing scheme [6] are also proposed to minimize the number of TSV, but they increase the design complexity and chip area due to adding a TSV arbiter module in router. [7] remove part of links and share vertical links to augment the yield of 3D topology and power consumption efficiency, but it's network performance become worse with the vertical links trimmed down to 75%.…”

Section: Related Workmentioning

confidence: 99%

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A 3D topology based-on partial overlapped clusters for NoC

Yang

et al. 2014

IEICE Electron. Express

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Three-dimensional (3D) topology of Network-On-Chip (NoC) has become a promising way to solve the problem of IP core scale expansions. It offers greater device integration and also can provide higherbandwidth, lower-latency and lower-consumption inter-layer communication with the help of through-silicon-vias (TSVs). However, the low yield of TSV and high overhead become a primary problems. In order to obtain better performance at relatively lower cost, this letter proposes a new 3D topology based-on Partial Overlapped Clusters (POC) for NoC, which reduces the number of routers and TSVs by sharing part of vertical links flexibly. We evaluate the proposed topology through performance analysis and simulations, the results demonstrate it can reduce the overhead distinctly and provide satisfactory performance.

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Section: Simulation Results and Performance Analysismentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

A 3D topology based-on partial overlapped clusters for NoC

Yang

et al. 2014

IEICE Electron. Express

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“…Our 3D stacking cost model is based on information obtained either from our industrial partner, or from some publications that deals with 3D IC cost analysis such as Ref. [11] of John H. Lau from the Industrial Technology Research Institute of Taiwan.…”

Section: D Stacking Cost Modelmentioning

confidence: 99%

A Stackable LTE Chip for Cost-effective 3D Systems

Lafi

Lattard

Jerraya

2012

IPSJ Transactions on System LSI Design Methodology

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Abstract:To address the problem of prohibitive cost of advanced fabrication technologies, one solution consists in reusing masks to address a wide range of ICs. This could be achieved by a modular circuit that can be stacked to build TSV-based 3D systems with processing performance adapted to several applications. This paper focuses on 4G wireless telecom applications. We propose a basic circuit that meets the SISO (Single Input Single Output) transmission mode. By stacking multiple instances of this same circuit, it will be possible to address several MIMO (Multiple Input Multiple Output) modes. The proposed circuit is composed of several processing units interconnected by a 3D NoC and controlled by a host processor. Compared to a 2D reference platform, the proposed circuit keeps at least the same performance and power consumption in the context of 4G telecom applications, while reducing total cost. More generally, our cost analysis shows that 3D integration efficiency depends on the size of the circuit and the stacking option (die-to-die, die-to-wafer and interposer-based stacking).

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“…Lau J.H. [10][11][12] presented an origin of 3D integration, discussed the evolution, challenges, and outlook of 3D IC/Si integrations, and proposed a few generic, low-cost, and thermal-enhanced 3D IC integration system-in-packages with various passive TSV interposes. Yen Y.G [13] elaborated the effect of TSV parameters on the thermal equivalent conductivity of TSV interposer , and studied the effect of TSV interposer on thermal performance of the package based on the objective of compact modeling.…”

Section: Introductionmentioning

confidence: 99%

Study on the Thermal Transient Response of TSV Considering the Effect of Electronic-Thermal Coupling

Li¹,

Zou²,

Shang³

et al. 2015

JSTS:Journal of Semiconductor Technology and Science

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Abstract-The transmission performance of TSV considering the effect of electronic-thermal coupling is an new challenge in three dimension integrated circuit. This paper presents the thermal equivalent circuit (TEC) model of the TSV, and discussed the thermal equivalent parameters for TSV. Si layer is equivalent to transmission line according to its thermal characteristic. Thermal transient response (TTR) of TSV considering electronic-thermal coupling effects are proposed, iteration flow electronic-thermal coupling for TSV is analyzed. Furthermore, the influences of TTR are investigated with the noncoupling and considering coupling for TSV. Finally, the relationship among temperature, thickness of SiO 2 , radius of via and frequency of excitation source are addressed, which are verified by the simulation.

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TSV manufacturing yield and hidden costs for 3D IC integration

Cited by 121 publications

References 37 publications

A 3D topology based-on partial overlapped clusters for NoC

A 3D topology based-on partial overlapped clusters for NoC

A Stackable LTE Chip for Cost-effective 3D Systems

Study on the Thermal Transient Response of TSV Considering the Effect of Electronic-Thermal Coupling

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